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Code Activity
4997 commits 124 branches 59 tags 44 MiB
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124 commits

Author SHA1 Message Date
Clifford Wolf
9474928672 Towards Xilinx bram support 2015-01-06 15:26:33 +01:00
Clifford Wolf
081e1a49f8 Towards Xilinx bram support 2015-01-06 14:26:51 +01:00
Clifford Wolf
9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b Towards Xilinx bram support 2015-01-04 14:23:30 +01:00
Clifford Wolf
daae35319b Added memory_bram "shuffle_enable" feature 2015-01-04 13:14:30 +01:00
Clifford Wolf
5d631f0ea7 Removed left over debug code from memory_bram 2015-01-04 11:46:04 +01:00
Clifford Wolf
45918b8315 Added "memory -bram" 2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888 Added memory_bram 'or_next_if_better' feature 2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04 memory_bram transp support 2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf
bbf89c4dc6 Progress in memory_bram 2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede Progress in memory_bram 2015-01-02 00:07:44 +01:00
Clifford Wolf
f29f4e7c83 Progress in memory_bram 2015-01-01 15:32:37 +01:00
Clifford Wolf
17c1c55473 Progress in memory_bram 2015-01-01 12:17:19 +01:00
Clifford Wolf
327a5d42b6 Progress in memory_bram 2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736 Added memory_bram (not functional yet) 2014-12-31 16:53:53 +01:00
Clifford Wolf
6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf
edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf
4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
ae02d9cb9a Fixed $memwr/$memrd order in memory_dff 2014-09-16 12:40:58 +02:00
Ruben Undheim
79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf
6ff46323a3 Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
Clifford Wolf
66763fad4e Using worker class in memory_map 2014-08-30 17:39:08 +02:00
Clifford Wolf
b4f10e342c Various improvements in memory_dff pass 2014-08-06 14:31:38 +02:00
Clifford Wolf
04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf
b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf
d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf
32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf
cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf
6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf
c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf
4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf
ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf
28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00