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Code Activity
12978 commits 92 branches 52 tags 62 MiB
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10 commits

Author SHA1 Message Date
Catherine c7bf0e3b8f Add new $check cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Catherine 1159e48721 write_verilog: emit initial $display correctly. 2024-01-11 13:13:04 +01:00
Charlotte f9d38253c5 ast: add PRIORITY to $print cells 2023-08-11 04:46:52 +02:00
Charlotte 843ad9331b cxxrtl: WIP: adjust comb display cells to only fire on change 
Naming and use of statics to be possibly revised.
 2023-08-11 04:46:52 +02:00
Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
 2023-08-11 04:46:52 +02:00
Charlotte c391ee7a0d docs: document simulation time format specifiers 2023-08-11 04:46:52 +02:00
Charlotte 202c3776e2 docs: elaborate $print documentation 2023-08-11 04:46:52 +02:00
Charlotte 2d7b8f71cc docs: first pass $print documentation 2023-08-11 04:46:52 +02:00
Charlotte 0c0171bd60 docs: RD_DATA is an output, not input 2023-06-21 17:21:04 +10:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496) 
Rst docs conversion
 2022-11-15 12:55:22 +01:00