Krystine Sherwin
cdb20baf1f
quicklogic: testing port widths on split rams
2023-11-30 17:33:13 +01:00
Krystine Sherwin
4c03c84fa7
quicklogic: testing 1:4 assymetric memory
2023-11-30 17:33:13 +01:00
Krystine Sherwin
a1073c706e
quicklogic: fix double width read
2023-11-30 17:33:13 +01:00
Krystine Sherwin
fbf8607b97
quicklogic: Testing split TDP36K
...
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-11-30 17:33:13 +01:00
Krystine Sherwin
0cd67ce473
quicklogic: Initial blockram tests
...
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-11-30 17:33:13 +01:00
Martin Povišer
fb34167fd4
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 13:43:56 +01:00
Martin Povišer
d11a85fcba
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 11:12:55 +01:00
Martin Povišer
193144e68b
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 10:45:39 +01:00
Martin Povišer
e70122b74e
fixup! quicklogic: Add basic k6n10f tests
2023-11-29 11:20:16 +01:00
Martin Povišer
5bc587c843
quicklogic: Add k6n10f DSP test
2023-11-27 17:43:21 +01:00
Martin Povišer
502559cba4
quicklogic: Fix dffs.ys test
2023-11-27 17:27:46 +01:00
Martin Povišer
a3b3333eeb
quicklogic: Add basic k6n10f tests
2023-11-27 12:14:48 +01:00
Martin Povišer
74296e3d92
quicklogic: Move pp3 tests one level down
2023-11-27 12:05:55 +01:00
N. Engelhardt
e230a871be
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
...
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Marcelina Kościelnicka
4a35f244aa
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
...
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
