Krystine Sherwin
0327ad97f2
Docs: Fix code formatting
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Gets me everytime
2024-08-22 10:03:59 +12:00
Krystine Sherwin
36ad07e1d5
Docs: Update build_verific
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Clarify partially supported builds section.
Update parameter defaults.
Include note on finding compile options with `yosys-config`.
Fix remaining references to `/yosys_source/`.
2024-08-22 10:03:59 +12:00
Krystine Sherwin
88bb785dcd
Docs: Verific but with sentences
2024-08-22 10:03:59 +12:00
Krystine Sherwin
cfba26ca8b
Docs: Verific progress
2024-08-22 10:03:59 +12:00
Krystine Sherwin
00bb3b6fc2
Docs: Merge yosys_source into extending_yosys
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Move abc_flow content into synthesis/abc document.
2024-08-22 10:03:59 +12:00
Krystine Sherwin
8e618cac45
Docs: Update build_verific.rst
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Move patch section to top.
Add todos for open questions.
Reformat partially supported builds into a single table.
General language tidy up/reflow.
2024-08-22 10:03:59 +12:00
Krystine Sherwin
53b223f0df
Docs: Initial build_verific.rst
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From verific.md
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
2024-08-22 10:03:59 +12:00
Krystine Sherwin
d97a243c22
Docs: Intro to Yosys source section
2024-08-22 10:03:59 +12:00
Krystine Sherwin
e18a2f1e27
Docs: Section/folder for yosys source details
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Move test_suites page into said folder.
Placeholder page for building with verific.
2024-08-22 10:03:58 +12:00
Krystine Sherwin
2ffafadf22
Docs: Add note on verific
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Having a verific license does not provide access to the verific frontend.
2024-08-22 10:03:58 +12:00
Roland Coeurjoly
27c1432253
Remove log
2024-08-21 14:28:42 +01:00
Roland Coeurjoly
91e3773b51
Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
2024-08-21 14:28:42 +01:00
Akash Levy
dba9a26cf3
Make default macros optional
2024-08-21 00:50:10 -07:00
Akash Levy
e2957936e4
Merge branch 'YosysHQ:main' into master
2024-08-20 01:38:01 -07:00
Akash Levy
58b3881845
Undo silly Yosys removal
2024-08-20 01:25:21 -07:00
Akash Levy
00d1ede702
Update Verific
2024-08-20 01:05:50 -07:00
Akash Levy
25476f7ce4
Fix again
2024-08-20 00:36:57 -07:00
Akash Levy
b6fc7e85d4
Update Verific
2024-08-20 00:35:36 -07:00
Akash Levy
6cb3c3217c
Update Yosys to remove unnecessary passes
2024-08-19 21:45:29 -07:00
github-actions[bot]
4cddc19994
Bump version
2024-08-20 00:18:24 +00:00
Akash Levy
56cfcdb9f6
Merge branch 'YosysHQ:main' into master
2024-08-19 17:12:02 -07:00
Miodrag Milanović
e4c8bb0ac5
Merge pull request #4552 from YosysHQ/krys/rtd_on_main
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docs: Only trigger RTDs on main
2024-08-19 20:11:55 +02:00
Krystine Sherwin
7d779c64a3
docs: Only trigger RTDs on main
2024-08-20 04:26:58 +12:00
Emil J
d901b28d2c
Merge pull request #4546 from NachtSpyder04/main
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[Docs]:Add new cell type help messages
2024-08-19 15:50:41 +02:00
Emil J
9de534892e
Merge pull request #4515 from RCoeurjoly/nix_on_macos
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Run nix build also on macos. Build with more logs
2024-08-19 15:49:23 +02:00
Emil J
e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix
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peepopt: avoid shift-amount underflow
2024-08-19 15:45:46 +02:00
Emil J
0dfa4962d1
Merge pull request #4547 from leviathanch/fix_apicula1
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Add DQS and related primitives to Gowin tech files
2024-08-19 15:44:48 +02:00
Emil J. Tywoniak
4847caac49
driver: print maximum memory usage on macOS as well
2024-08-19 12:50:12 +02:00
Krystine Sherwin
6df0c3d9ec
docs: Fix synth_flow generation
2024-08-19 21:25:51 +12:00
Krystine Sherwin
8773cf7721
test-verific: Use fast runner
2024-08-19 21:24:48 +12:00
N. Engelhardt
7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd
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Local readthedocs
2024-08-19 10:04:38 +02:00
David Lanzendörfer
d1b767ea8b
Adding missing to Gowin tech files
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Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
2024-08-18 19:38:31 +01:00
NachtSpyder04
aa60255e0e
update help messages that went beyond line length limit
2024-08-18 20:27:35 +05:30
Saish Karole
34aabd56cc
Apply suggestions from code review
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Co-authored-by: Martin Povišer <povik@cutebit.org>
2024-08-18 20:12:53 +05:30
Saish Karole
d80d4dc51c
[Docs]:Add new cell type help messages ( #1 )
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* add shift operators description
* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
2024-08-17 15:47:00 +05:30
github-actions[bot]
5fb3c0b1d9
Bump version
2024-08-17 00:17:44 +00:00
KrystalDelusion
3dd32d741a
Stop unconditionally building abc
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_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.
_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite. It still runs as before, but no longer triggers yosys-abc to rebuild when it does.
_If applicable, please suggest to reviewers how they can test the change._
2024-08-17 11:04:17 +12:00
Krystine Sherwin
e9f909aa25
minisat: Record changes in patch
2024-08-17 10:01:25 +12:00
Krystine Sherwin
7bd3c7b968
Fix test-verific.yml
2024-08-16 10:43:51 +12:00
Krystine Sherwin
3b63ab07ae
docs: Build RTD artifacts directly
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Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
2024-08-16 10:43:51 +12:00
Krystine Sherwin
55307a5452
minisat: Check for gcc
2024-08-16 04:30:37 +12:00
Krystine Sherwin
eb02ab07da
minisat: Use reallocarray
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Avoid gcc warning about non-trivial copying.
2024-08-16 04:30:37 +12:00
Krystine Sherwin
d34833d177
Better snprintf size handling
2024-08-16 04:30:37 +12:00
Krystine Sherwin
636ce9ac2c
snprintf
2024-08-16 04:30:36 +12:00
Krystine Sherwin
7b47f645d7
Address warnings
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- Setting default values
- Fixing mismatched types
- Guarding unused var
2024-08-16 04:30:31 +12:00
Miodrag Milanovic
54d237ff82
add min_ce_use and min_srst_use parameters
2024-08-15 17:50:36 +02:00
Miodrag Milanovic
14e43139cb
Run opt_merge, helps with inverted reset/load signals
2024-08-15 17:50:36 +02:00
Miodrag Milanovic
220ddeac4d
Set -mince and -minsrst
2024-08-15 17:50:36 +02:00
Miodrag Milanovic
dbf1d037e8
Cleanup
2024-08-15 17:50:36 +02:00
Miodrag Milanovic
7bf623a0c7
Fix simulation model warnings
2024-08-15 17:50:36 +02:00
