mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 11:25:53 +00:00
Code Activity
14781 commits 101 branches 53 tags 48 MiB
Commit graph

3 commits

Author SHA1 Message Date
Emil J. Tywoniak
4cbc92f50f quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fcdd013c57 quicklogic: allow fractured mode on canonical dspv1 modules 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
c451d8ebb9 synth_quicklogic: add -dspv2 to opt into v2 DSP blocks 2025-03-11 10:35:30 +01:00
Renamed from techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v (Browse further)