3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 21:38:45 +00:00
Commit graph

2 commits

Author SHA1 Message Date
Eddie Hung b71212ddea Add BRAM arrival times 2019-08-19 12:46:35 -07:00
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Renamed from techlibs/xilinx/brams_bb.v (Browse further)