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Author SHA1 Message Date
Miodrag Milanović
c6caadfed4
Merge pull request #3902 from YosysHQ/krys/yw_join 
yosys-witness concat yw trace files
 2023-08-25 15:21:44 +02:00
Miodrag Milanović
1b6d803877
Merge pull request #3900 from YosysHQ/micko/synth_lattice 
Create unified synth_lattice
 2023-08-25 12:44:30 +02:00
Miodrag Milanovic
0756285710 enable more primitives supported with nextpnr 2023-08-25 11:45:25 +02:00
Miodrag Milanovic
3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic
541c1ab567 add script for blackbox extraction 2023-08-23 11:51:00 +02:00
Miodrag Milanovic
ea50d96135 fixed tests 2023-08-23 10:54:29 +02:00
Miodrag Milanovic
75fd706487 delete machxo2 since it is now supported in lattice 2023-08-23 10:54:17 +02:00
Miodrag Milanovic
e3c15f003e Create synth_lattice 2023-08-23 10:53:21 +02:00
Miodrag Milanovic
a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
github-actions[bot]
6405bbab1e Bump version 2023-08-18 00:14:07 +00:00
Asherah Connor
4a475fa7a2 cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
Ethan Mahintorabi
d525a41497
abc: Exposes dont_use flag in ABC 
ABC's read_lib command has a dont_use
cell list that is configurable by the user.

This PR exposes that option to Yosys.

See
5405d4787a/src/map/scl/scl.c (L285)
for documentation on this option.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-08-15 20:03:46 +00:00
github-actions[bot]
cbd3ff2d3a Bump version 2023-08-15 00:14:23 +00:00
Miodrag Milanović
316200493e
Merge pull request #3889 from povik/cellaigs-fix-gcc9-build 
cellaigs: Drop initializer list in call to `IdString::in`
 2023-08-14 16:05:57 +02:00
Martin Povišer
6d9cd16fad cellaigs: Drop initializer list in call to IdString::in 
Remove superfluous curly braces in call to IdString::in to address
a compilation error (reproduced below) under GCC 9 and earlier.

kernel/cellaigs.cc:395:18: error: call to member function 'in' is ambiguous
if (cell->type.in({ID($gt), ID($ge)}))
~~~~~~~~~~~^~
./kernel/rtlil.h:383:8: note: candidate function
bool in(const std::string &rhs) const { return *this == rhs; }
^
./kernel/rtlil.h:384:8: note: candidate function
bool in(const pool &rhs) const { return rhs.co...
^
 2023-08-14 11:42:19 +02:00
Krystine Sherwin
e2c0f8fc50
Some tidy up 2023-08-14 12:13:29 +12:00
github-actions[bot]
008b725c1d Bump version 2023-08-13 00:15:02 +00:00
Charlotte
d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
Charlotte
860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte
bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
github-actions[bot]
40978971f4 Bump version 2023-08-12 00:13:32 +00:00
Charlotte
2829cd9caa cxxrtl_backend: move sync $print grouping out of dump into analyze 2023-08-11 04:46:52 +02:00
Charlotte
ce245b5105 cxxrtl_backend: respect sync $print priority 
We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs.  We could probably move this grouping out of
the dump method.
 2023-08-11 04:46:52 +02:00
Charlotte
04582f2fb7 verilog_backend: emit sync $print cells with same triggers together 
Sort by PRIORITY, ensuring output order.
 2023-08-11 04:46:52 +02:00
Charlotte
f9d38253c5 ast: add PRIORITY to $print cells 2023-08-11 04:46:52 +02:00
Charlotte
4ffdee65e0 cxxrtl: store comb $print cell last EN/ARGS in module 
statics were obviously wrong -- may be multiple instantiations of any
given module.  Extend test to cover this.
 2023-08-11 04:46:52 +02:00
Charlotte
843ad9331b cxxrtl: WIP: adjust comb display cells to only fire on change 
Naming and use of statics to be possibly revised.
 2023-08-11 04:46:52 +02:00
Charlotte
7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
 2023-08-11 04:46:52 +02:00
Charlotte
eb0fb4d662 tests: -std=c++11 not optional 2023-08-11 04:46:52 +02:00
Charlotte
992a728ec7 tests: CXX may be e.g. gcc, so use CC and link stdc++ explicitly 2023-08-11 04:46:52 +02:00
Charlotte
4e94f62116 simlib: blackbox $print cell 
It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
 2023-08-11 04:46:52 +02:00
Charlotte
fc0acd0ad1 cxxrtl: restrict -print-output to cout, cerr 2023-08-11 04:46:52 +02:00
Charlotte
f9b149fa7b cxxrtl: add "-print-output" option, test in fmt 2023-08-11 04:46:52 +02:00
Charlotte
bfa8b631bf cxxrtl: remove unused signedDivideWithRemainder 2023-08-11 04:46:52 +02:00
Charlotte
a1de898fcc fmt: merge fuzzers since we don't rely on BigInteger logic 
This is per fmt's (effective) use, as it turns out, so we're not losing
any fidelity in the comparison.
 2023-08-11 04:46:52 +02:00
Charlotte
3571bf2c2d fmt: fuzz, remove some unnecessary busywork 
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
 2023-08-11 04:46:52 +02:00
Charlotte
2ae551c0af fmt: fuzz, fix (remove extraneous + incorrect fill) 
"blk + chunks" is often an overrun, plus the fill is unnecessary; we
throw blk away immediately.
 2023-08-11 04:46:52 +02:00
Charlotte
9f9561379b fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
Charlotte
c391ee7a0d docs: document simulation time format specifiers 2023-08-11 04:46:52 +02:00
Charlotte
75b44f21d1 fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
Charlotte
c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
Charlotte
52dc397a50 cxxrtl: don't use signed divide with unsigned/pos values 
Incorrect for unsigned, wasted effort for positive signed.
 2023-08-11 04:46:52 +02:00
Charlotte
b0f69f2cd5 tests: test cxxrtl against iverilog (and uncover bug!) 2023-08-11 04:46:52 +02:00
Charlotte
095b093f4a cxxrtl: first pass of $print impl 2023-08-11 04:46:52 +02:00
Charlotte
202c3776e2 docs: elaborate $print documentation 2023-08-11 04:46:52 +02:00
Charlotte
d9e4582558 fmt: handle part with unspecified padding in emit_rtlil 
e.g. `$displayh(8'ha)` won't have a padding set, because it just gets
`lzero` set instead by `compute_required_decimal_places`.

It also doesn't have a width.  In this case, we can just fill in a dummy
(unused) padding.  Either space or zero would work, but space is a bit
more distinct given the width field follows.

Also omit writing the width if it's zero.  This makes the emitted ilang
a little cleaner in places; `{8:> h0u}` is the output for this example,
now.  The other possible extreme would be `{8:>00h0u}`.
 2023-08-11 04:46:52 +02:00
Charlotte
1a222cb163 fmt: function name typo 2023-08-11 04:46:52 +02:00
Charlotte
2d7b8f71cc docs: first pass $print documentation 2023-08-11 04:46:52 +02:00
Charlotte
289f8d42cb fmt: correct parsing of {{ and }} for brace literals 2023-08-11 04:46:52 +02:00
Charlotte
3c8f84b70b fmt: fix another overrun 2023-08-11 04:46:52 +02:00