180 commits

Author	SHA1	Message	Date
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	4755e14e7b	Added copy-constructor-like module->addCell(name, other) method	2014-07-26 00:38:44 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	8d04ca7d22	Added call_on_selection() and call_on_module() API	2014-07-20 15:33:06 +02:00
Clifford Wolf	744e518467	fixed cell array handling of positional arguments	2014-06-07 12:17:11 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	6644f80d97	Moved some passes to other source directories	2014-02-08 14:39:15 +01:00
Clifford Wolf	7a5f378bae	Added hierarchy -purge_lib option	2014-02-04 16:50:13 +01:00
Martin Schmölzer	aa17f16fec	Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) ... This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>	2014-01-14 20:12:45 +01:00
Clifford Wolf	0c5b1f32d4	Added hierarchy -libdir option	2014-01-14 19:28:20 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	f7f0af6f9c	Added resolution of positional arguments to hierarchy pass	2013-11-03 09:42:51 +01:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	b11d9408d9	Improved log messages generated by hierarchy pass	2013-05-26 12:20:51 +02:00
Clifford Wolf	94744ac7b0	Fixed hierarchy pass for hierarchies of parametric modules	2013-04-26 13:28:15 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	6a231816fa	Collect parameters in hierarchy -generate (and do nothing with them)	2013-03-26 19:11:53 +01:00
Clifford Wolf	4a7d624bef	Added hierarchy -generate command for generating skeletton modules	2013-03-25 02:14:33 +01:00
Clifford Wolf	4fcb9a7b99	Implemented general handler for selection arguments	2013-03-03 10:05:37 +01:00
Clifford Wolf	af561800ed	Added online help for "show" and "hierarchy" commands	2013-02-28 13:59:49 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00