Lofty
8cc9aa7fc6
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
gatecat
eb106732d9
intel_alm: Add global buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
5dba138c87
intel_alm: Add IO buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Dan Ravensloft
0d4c2f0a65
intel_alm: add Cyclone 10 GX tests
2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07
tests: update fsm.ys resource count
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Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862 ?
2020-07-04 19:45:10 +02:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
