Clifford Wolf
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a76189e7ad
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More opt_clean cleanups
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-07 14:41:58 +02:00 |
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Clifford Wolf
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752553d8e9
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Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
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2019-05-06 20:57:15 +02:00 |
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Clifford Wolf
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1706798f4e
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Merge pull request #975 from YosysHQ/clifford/fix968
Re-enable "final loop assignment" feature and fix opt_clean warnings
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2019-05-06 20:53:38 +02:00 |
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Clifford Wolf
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7bab7b3d49
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Merge pull request #871 from YosysHQ/verific_import
Improve verific -chparam and add hierarchy -chparam
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2019-05-06 20:51:59 +02:00 |
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Clifford Wolf
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d187be39d6
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
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2019-05-06 15:41:13 +02:00 |
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Clifford Wolf
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b37c31e2cb
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Bugfix in peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 15:34:19 +02:00 |
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Clifford Wolf
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c0782d8390
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Merge pull request #989 from YosysHQ/dave/abc_name_improve
ABC name recovery fixes
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2019-05-06 13:57:35 +02:00 |
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Clifford Wolf
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f02e22a35a
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Fix bug in "expose -input"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 13:30:55 +02:00 |
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Clifford Wolf
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ba6ce21a74
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Cleanups in opt_clean
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-06 12:45:22 +02:00 |
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Clifford Wolf
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c7f2e93024
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
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2019-05-06 11:46:10 +02:00 |
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David Shah
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a84256aa36
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abc: Fix handling of postfixed names (e.g. for retiming)
Signed-off-by: David Shah <dave@ds0.me>
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2019-05-04 17:23:44 +01:00 |
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David Shah
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5ce9113eda
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abc: Improve name recovery
Signed-off-by: David Shah <dave@ds0.me>
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2019-05-04 16:53:25 +01:00 |
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Clifford Wolf
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a01386c0e4
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Improve opt_clean handling of unused wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 09:47:16 +02:00 |
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Eddie Hung
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d9c4644e88
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Merge remote-tracking branch 'origin/master' into clifford/specify
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2019-05-03 15:05:57 -07:00 |
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Clifford Wolf
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ec39cfd0ad
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Add "hierarchy -chparam" support for non-verific top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 22:03:43 +02:00 |
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Eddie Hung
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eb21bf3651
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log_warning_noprefix -> log_warning as per review
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2019-05-03 20:53:25 +02:00 |
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Eddie Hung
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a27b42e975
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WIP -chparam support for hierarchy when verific
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2019-05-03 20:53:25 +02:00 |
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Clifford Wolf
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373b236108
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
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2019-05-03 20:39:50 +02:00 |
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Clifford Wolf
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f170fb6383
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Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
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2019-05-03 20:34:32 +02:00 |
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Eddie Hung
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e08df0c739
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If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03 08:06:16 -07:00 |
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Eddie Hung
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fc349de033
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Revert "dffinit -noreinit to silently continue when init value is 1'bx"
This reverts commit aa081f83c7.
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2019-05-03 08:05:37 -07:00 |
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Clifford Wolf
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42190207b4
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Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 14:25:01 +02:00 |
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Clifford Wolf
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5c2c0b4bb2
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Further improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:22:26 +02:00 |
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Clifford Wolf
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f12e1155f1
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Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:12:10 +02:00 |
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Clifford Wolf
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2b29aa5c86
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:35:45 +02:00 |
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Clifford Wolf
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e8c5afcb84
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:25:30 +02:00 |
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Eddie Hung
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aa081f83c7
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dffinit -noreinit to silently continue when init value is 1'bx
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2019-05-02 17:40:39 -07:00 |
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Eddie Hung
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f86d153cef
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Merge branch 'master' of github.com:YosysHQ/yosys
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2019-05-01 16:26:43 -07:00 |
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Clifford Wolf
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521663f09e
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Add missing enable_undef to "sat -tempinduct-def", fixes #883
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-02 00:03:31 +02:00 |
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Clifford Wolf
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93b7fd7744
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Fix floating point exception in qwp, fixes #923
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 15:06:46 +02:00 |
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Clifford Wolf
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a30b99e66e
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Silently resolve completely unused cell-vs-const driver-driver conflicts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:29:34 +02:00 |
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Clifford Wolf
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32ff37bb5a
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Fix segfault in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 22:20:45 +02:00 |
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Clifford Wolf
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a27eeff573
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Merge pull request #966 from YosysHQ/clifford/fix956
Drive dangling wires with init attr with their init value
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2019-04-30 18:08:41 +02:00 |
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Clifford Wolf
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9d117eba9d
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Add handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 14:46:12 +02:00 |
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Clifford Wolf
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b515fd2d25
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Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 11:25:15 +02:00 |
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Clifford Wolf
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4306bebe58
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pmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 10:51:51 +02:00 |
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Clifford Wolf
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bb4f3642de
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Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 08:04:22 +02:00 |
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Clifford Wolf
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58238da133
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Progress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 07:59:39 +02:00 |
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Clifford Wolf
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ea547bcaa3
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Add "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:38:56 +02:00 |
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Clifford Wolf
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9f792c599d
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Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:02:05 +02:00 |
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Clifford Wolf
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32881a989c
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Support multiple pmg files (right now just concatenated together)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 12:09:02 +02:00 |
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Clifford Wolf
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754b1ee4b3
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Drive dangling wires with init attr with their init value, fixes #956
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2019-04-29 08:44:53 +02:00 |
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Eddie Hung
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acafcdc94d
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Copy with 1'bx padding in $shiftx
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2019-04-28 13:04:34 -07:00 |
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Eddie Hung
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159e7cc298
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Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-26 11:16:48 -07:00 |
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Eddie Hung
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408161ea3a
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Misspelling
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2019-04-25 16:46:13 -07:00 |
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Clifford Wolf
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71c38d9de5
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Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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634482380c
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Preserve $specify[23] cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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c84cdc711c
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Remove some left-over log_dump()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 17:55:41 +02:00 |
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Eddie Hung
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d9daf09cf3
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Merge pull request #914 from YosysHQ/xc7srl
synth_xilinx to now infer SRL16E/SRLC32E
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2019-04-22 13:31:30 -07:00 |
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Clifford Wolf
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8ed4a53d99
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Merge pull request #951 from YosysHQ/clifford/logdebug
Add log_debug() framework
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2019-04-22 20:09:51 +02:00 |
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