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5745 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
6a57de9013 write_xaiger to support non-bit cell connections, and cope with COs for -O 2019-02-16 21:00:39 -08:00
Eddie Hung
f853b2f3c1 abc9 to write_aiger with -O option, and ignore dummy outputs 2019-02-16 20:09:40 -08:00
Eddie Hung
b9a305b85d write_aiger -O to write dummy output as __dummy_o__ 2019-02-16 20:08:59 -08:00
Eddie Hung
d8c4d4e6c7 abc9 to handle comb loops, cope with constant outputs, disconnect using new wire 2019-02-16 13:47:38 -08:00
Eddie Hung
1a25ec4baa read_aiger to disable log_debug 2019-02-16 13:45:51 -08:00
Eddie Hung
e7c7ab8fc0 expose command to not skip 'internal' wires beginning with '$' 2019-02-16 13:45:17 -08:00
Eddie Hung
8f36013fac read_xaiger() to use f.read() not readsome() 2019-02-16 08:58:25 -08:00
Eddie Hung
d4545d415b abc9 to cope with non-wideports, count cells properly 2019-02-16 08:53:06 -08:00
Eddie Hung
0c409e6d8c Tidy up write_xaiger 2019-02-16 08:48:33 -08:00
Eddie Hung
2c1655ae94 write_aiger() to perform CI/CO post-processing and fix symbols 2019-02-16 08:46:25 -08:00
Eddie Hung
7523c87780 read_aiger() to cope with constant outputs, mixed wideports, do cleaning 2019-02-16 08:44:11 -08:00
Eddie Hung
f8d0134598 Move lookup inside if 2019-02-15 15:23:26 -08:00
Eddie Hung
486a270415 Fixes needed for DFF circuits 2019-02-15 15:22:18 -08:00
Eddie Hung
a786ac4d53 Refactor 2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9 Cope with width != 1 when re-mapping cells 2019-02-15 12:55:52 -08:00
Jim Lawson
c245041bfe Removed unused variables, functions. 2019-02-15 12:00:28 -08:00
Jim Lawson
34153adef4 Append (instead of over-writing) EXTRA_FLAGS 2019-02-15 11:56:51 -08:00
Eddie Hung
956ee545c5 abc9 to stitch results with CI/CO properly 2019-02-15 11:52:34 -08:00
Eddie Hung
8d757224ee read_aiger with more asserts, and call clean 2019-02-15 11:52:05 -08:00
Eddie Hung
3ac5b65197 write_xaiger to cope with unknown cells by transforming them to CI/CO 2019-02-15 11:51:21 -08:00
Jim Lawson
5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
Jim Lawson
fc1c9aa11f Update cells supported for verilog to FIRRTL conversion. 
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
 2019-02-15 11:14:17 -08:00
Jim Lawson
970f854c2a Merge remote-tracking branch 'upstream/master' 2019-02-15 08:19:27 -08:00
Eddie Hung
c69fba8de5 More cleanup 2019-02-14 14:52:47 -08:00
Eddie Hung
7328775584 More cleanup of write_xaiger 2019-02-14 14:48:38 -08:00
Eddie Hung
afa4389445 Get rid of formal stuff from xaiger backend 2019-02-14 13:27:26 -08:00
Eddie Hung
323dd0e608 synth_ice40 to have new -abc9 arg 2019-02-14 13:19:27 -08:00
Eddie Hung
c7ef3863f3 Leave FIXME for clean 2019-02-13 17:19:30 -08:00
Eddie Hung
396da54b52 Use module->addLut() 2019-02-13 17:08:32 -08:00
Eddie Hung
206f11dca3 Fix stitching 2019-02-13 17:04:23 -08:00
Eddie Hung
13bf036bd6 Use ConstEval to compute LUT masks 2019-02-13 17:00:00 -08:00
Eddie Hung
f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee Merge https://github.com/YosysHQ/yosys into xaig 2019-02-13 14:08:31 -08:00
Eddie Hung
87f059adf7 Rip out some more stuff 2019-02-13 10:44:52 -08:00
Clifford Wolf
807b3c7697 Fix sign handling of real constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-13 12:36:47 +01:00
David Shah
e0bc190879 ecp5: Add ECLKSYNCB blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-13 11:23:25 +00:00
Eddie Hung
045f7763ae Rip out unused functions in abc9 2019-02-12 16:25:22 -08:00
Eddie Hung
e9df9a466a Add support for read_aiger -wideports 2019-02-12 12:58:10 -08:00
Eddie Hung
06ba81d41f Add support for read_aiger -map 2019-02-12 12:16:37 -08:00
Eddie Hung
77d3627753 Parse 'm' in xaiger 2019-02-12 09:36:22 -08:00
Eddie Hung
b3341b4abb WIP for ABC with aiger 2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751 Missing headers for Xcode? 2019-02-12 09:24:13 -08:00
Eddie Hung
6faad18874 Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger 2019-02-12 09:21:46 -08:00
Eddie Hung
a2ae393811 Use module->add{Not,And}Gate() functions 2019-02-12 09:21:15 -08:00
Clifford Wolf
1f2548a564
Merge pull request #802 from whitequark/write_verilog_async_mem_ports 
write_verilog: correctly emit asynchronous transparent ports
 2019-02-12 14:41:34 +01:00
Clifford Wolf
b9f6ed40b6
Merge pull request #806 from daveshah1/fsm_opt_no_reset 
fsm_opt: Fix runtime error for FSMs without a reset state
 2019-02-12 14:39:39 +01:00
David Shah
7913baedd8 ecp5: Full set of IO-related blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 12:04:41 +00:00
Eddie Hung
0124512f28 Add read_xaiger 2019-02-11 15:19:17 -08:00
Eddie Hung
ecd2446132 Add write_xaiger 2019-02-11 15:18:42 -08:00
Eddie Hung
04c580fde7 Do not break for constraints 2019-02-11 13:28:00 -08:00