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Code Activity
16151 commits 121 branches 60 tags 48 MiB
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5 commits

Author SHA1 Message Date
Lofty
b136a3c417 synth_analogdevices: update timing model and tests 2025-11-10 13:19:38 +00:00
Krystine Sherwin
09b5f610f7 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2025-11-09 15:44:35 +00:00
Lofty
0261d18759 analogdevices: DSP inference 2025-11-09 15:44:35 +00:00
Krystine Sherwin
b3f0d13c26 analogdevices: Update lutram.ys test 2025-11-09 15:44:34 +00:00
Lofty
9f26034176 test suite 2025-11-09 15:44:34 +00:00