16 commits

Author	SHA1	Message	Date
Lofty	b136a3c417	synth_analogdevices: update timing model and tests	2025-11-10 13:19:38 +00:00
Lofty	8101eca236	analogdevices: DSP tweaks	2025-11-09 15:44:35 +00:00
Lofty	0261d18759	analogdevices: DSP inference	2025-11-09 15:44:35 +00:00
Lofty	dd5fbebe8e	analogdevices: timings for t40lp	2025-11-09 15:44:35 +00:00
Lofty	47c5a52674	analogdevices: use single tech param	2025-11-09 15:44:35 +00:00
Lofty	4aa5008c56	analogdevices: expreso does not care about clock buffers	2025-11-09 15:44:35 +00:00
Lofty	3e1ca2f3e6	analogdevices: prepare for t40lp timings	2025-11-09 15:44:35 +00:00
Krystine Sherwin	dc76af06a0	analogdevices: Adding RBRAM2 and -tech	2025-11-09 15:44:34 +00:00
Krystine Sherwin	3f90865a28	analogdevices: (some) Native BRAM ... Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy). Drop the unused defines from the synth pass. Remove comments from the lutram files referencing xilinx.	2025-11-09 15:44:34 +00:00
Krystine Sherwin	d5074c5849	analogdevices: Native LUTRAM primitives	2025-11-09 15:44:34 +00:00
Lofty	a2983851f0	analogdevices: LUTRAM config	2025-11-09 15:44:34 +00:00
Lofty	2b384b8d53	analogdevices: update timing model	2025-11-09 15:44:34 +00:00
Lofty	a5271bc482	analogdevices: more housekeeping	2025-11-09 15:44:34 +00:00
Lofty	5abb8fd6f1	analogdevices: remove some extra cells!	2025-11-09 15:44:34 +00:00
Lofty	9f26034176	test suite	2025-11-09 15:44:34 +00:00
Lofty	f4c003b1c5	Create synth_analogdevices	2025-11-09 15:44:34 +00:00