Eddie Hung
261daffd9d
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-15 12:19:47 -07:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478
Add DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 10:21:24 -07:00
David Shah
edff79a25a
xilinx: Rework labels for faster Verilator testing
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
162eab6b74
Combine techmap calls
2019-08-08 10:55:48 -07:00
Eddie Hung
7160243874
Move xilinx_dsp to before alumacc
2019-08-08 10:45:56 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
fc0b5d5ab6
Change $__softmul back to $mul
2019-08-01 12:45:14 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Eddie Hung
5562cb08a4
Use single DSP_SIGNEDONLY macro
2019-07-18 13:09:55 -07:00
Eddie Hung
58e63feae1
Update comment
2019-07-17 13:26:17 -07:00
Eddie Hung
6390c535ba
Revert drop down to 24x16 multipliers for all
2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-16 14:18:36 -07:00
David Shah
95c8d27b0b
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:47:53 +01:00
Eddie Hung
5f00d335d4
Oops forgot these files
2019-07-15 15:03:15 -07:00
Eddie Hung
146451a767
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-15 09:49:41 -07:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
7b2599cb94
Move ABC FF stuff to abc_ff.v; add support for other FD* types
2019-07-10 17:06:05 -07:00
Eddie Hung
838ae1a14c
synth_xilinx's map_cells stage to techmap ff_map.v
2019-07-10 16:15:57 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
Eddie Hung
b33ecd2a74
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
2019-07-10 16:00:03 -07:00
Eddie Hung
cea7441d8a
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-10 15:58:01 -07:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
...
Error out if -abc9 and -retime specified
2019-07-10 14:38:13 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
e573d024a2
Call muxpack and pmux2shiftx before cmp2lut
2019-07-09 21:26:38 -07:00
Eddie Hung
c55530b901
Restore opt_clean back to original place
2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 14:28:54 -07:00
Eddie Hung
c68b909210
synth_xilinx to call commands of synth -coarse directly
2019-07-09 10:21:54 -07:00
Eddie Hung
737340327f
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
...
This reverts commit 7f964859ec
2019-07-09 10:15:02 -07:00
Eddie Hung
bc84f7dd10
Fix spacing
2019-07-09 09:22:12 -07:00
Eddie Hung
667199d460
Fix spacing
2019-07-09 09:16:00 -07:00
Eddie Hung
45da3ada7b
Do not call opt -mux_undef (part of -full) before muxcover
2019-07-08 23:49:16 -07:00
Eddie Hung
7f964859ec
synth_xilinx to call "synth -run coarse" with "-keepdc"
2019-07-08 19:23:24 -07:00
Eddie Hung
78914e2e0e
Capitalisation
2019-07-08 17:06:22 -07:00
Eddie Hung
baf47e496f
Add synth_xilinx -widemux recommended value
2019-07-08 17:04:39 -07:00
Eddie Hung
895ca50173
Fixes for 2:1 muxes
2019-07-08 12:03:38 -07:00
Eddie Hung
0944acf3af
synth_xilinx -widemux=2 is minimum now
2019-07-08 11:29:21 -07:00
David Shah
c865559f95
xc7: Map combinational DSP48E1s
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 19:15:25 +01:00
Eddie Hung
dbe1326573
Parametric muxcover costs as per @daveshah1
2019-07-08 11:08:20 -07:00
Eddie Hung
c58998a7d2
atoi -> stoi as per @daveshah1
2019-07-08 10:48:10 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
728839d6ca
Remove peepopt call in synth_xilinx since already in synth -run coarse
2019-06-28 12:53:38 -07:00
Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
312c03e4ca
Remove redundant doc
2019-06-27 15:28:55 -07:00
Eddie Hung
4d00e27ed7
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116
Add warning if synth_xilinx -abc9 with family != xc7
2019-06-27 11:22:49 -07:00
