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Code Activity
11071 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
c7fbe13db5 read_aiger: set abc9_box_seq attr 2020-01-24 13:11:43 -08:00
Eddie Hung
81e6b040a4 ice40: add SB_SPRAM256KA arrival time 2020-01-24 12:17:09 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
cccc0ae112 verific: unflatten struct ports 2020-01-24 10:12:52 -08:00
Eddie Hung
dbf351390e abc9: -reintegrate recover type from existing cell, check against boxid 2020-01-23 22:45:34 -08:00
Eddie Hung
2d795fb8c0 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
Eddie Hung
dca1c806ec simple_abc9 tests to discard whitebox before write for sim 2020-01-23 19:55:11 -08:00
Eddie Hung
e471b330ac abc_box_id -> abc9_box_id in test 2020-01-23 19:12:19 -08:00
Eddie Hung
245873d42d abc9: warning message if no modules selected 2020-01-23 19:08:51 -08:00
Eddie Hung
7858cf20a9 Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-23 19:02:27 -08:00
Eddie Hung
11e50c0e9e Test for (* keep *)-ed abc9_box_id 2020-01-23 18:56:25 -08:00
Eddie Hung
f180dba753 abc9_ops: -prep_xaiger to skip (* keep *) cells 2020-01-23 18:56:06 -08:00
Eddie Hung
48aec34e0d abc_box_id -> abc9_box_id in test 2020-01-23 18:53:14 -08:00
Eddie Hung
1d4314d888 abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_* 2020-01-23 14:58:56 -08:00
Eddie Hung
af0e7637a2 alumacc: undo accidental commit 2020-01-22 20:54:03 -08:00
Eddie Hung
da134701cd Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-22 14:22:03 -08:00
Eddie Hung
73526a6f10 read_aiger: also parse abc9_mergeability 2020-01-22 14:21:25 -08:00
Eddie Hung
8eb5bb258c Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor 2020-01-22 12:30:14 -08:00
Eddie Hung
da6abc0149
Merge pull request #1652 from YosysHQ/eddie/abc9_fixes 
Eddie/abc9 fixes
 2020-01-22 12:27:41 -08:00
Eddie Hung
a94b41011d abc9: error out if flip-flop init is 1'b1 for '-dff' 
Due to ABC sequential synthesis restriction
 2020-01-22 10:08:48 -08:00
Eddie Hung
3b44b53e94 abc9: fix scratchpad entry abc9.verify 2020-01-22 09:36:54 -08:00
Eddie Hung
5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung
72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung
3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung
152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung
cd093c00f8 read_aiger: discard LUT inputs with nodeID == 0; not < 2 2020-01-21 11:56:30 -08:00
Eddie Hung
7f728bc116 read_aiger: ignore constant inputs on LUTs 2020-01-21 11:16:50 -08:00
Eddie Hung
cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
Claire Wolf
5791c52e1b
Merge pull request #1637 from YosysHQ/mwk/fix-1634 
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
 2020-01-21 18:37:06 +01:00
Claire Wolf
30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z 
edif: Just ignore connections to 'z
 2020-01-21 18:35:15 +01:00
Claire Wolf
f165a74824
Merge pull request #1621 from YosysHQ/clifford/fminit 
Add fminit pass
 2020-01-20 22:01:57 +01:00
David Shah
22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map 
Cleanup +/xilinx/arith_map.v
 2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
 2020-01-18 09:47:17 +00:00
Eddie Hung
67c6bf0b6b
Merge pull request #1645 from YosysHQ/eddie/fix1644 
{ice40,xilinx}_dsp: improve robustess
 2020-01-17 19:25:59 -08:00
Eddie Hung
6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e xilinx_dsp: add parameter defaults 2020-01-17 16:05:10 -08:00
Eddie Hung
5507c328ff Add #1644 testcase 2020-01-17 15:57:52 -08:00
Eddie Hung
78ffd5d193 synth_ice40: call wreduce before mul2dsp 2020-01-17 15:41:55 -08:00
Eddie Hung
ad6c49fff1 ice40_dsp: add test 2020-01-17 15:38:26 -08:00
Eddie Hung
4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Eddie Hung
5c589244df Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
Eddie Hung
d4e188299b abc9: add some log_{push,pop}() as per @nakengelhardt 2020-01-17 12:00:14 -08:00
Eddie Hung
1e6d56dca1 +/xilinx/arith_map.v fix $lcu rule 2020-01-17 11:28:37 -08:00
Jeff Wang
98c6bd7630 fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 
The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
 2020-01-17 02:07:42 -05:00