166 commits

Author	SHA1	Message	Date
Clifford Wolf	42348cddd9	Merge pull request #63 from wluker/verilog-backend-mem ... Fixed bug in $mem cell verilog code generation.	2015-05-11 21:38:06 +02:00
luke whittlesey	3bb5f064b8	Fixed bug in $mem cell verilog code generation.	2015-05-11 14:05:18 -04:00
Clifford Wolf	9e56739634	Disabled broken $mem support in verilog backend	2015-05-10 21:38:41 +02:00
luke whittlesey	6de8fea2c7	Made changes recommended by Clifford Wolf ... ... Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.	2015-05-10 11:33:24 -04:00
luke whittlesey	2c1e150297	Verilog backend for $mem cells should now be able to handle different ... write-enable bits and RD_TRANSPARENT parameter settings.	2015-05-08 15:29:51 -04:00
luke whittlesey	c0b68f4848	Added support for $mem cells in the verilog backend.	2015-05-07 13:03:09 -04:00
Clifford Wolf	d176e613c2	Minor fixes in handling of "init" attribute	2015-04-09 15:12:26 +02:00
Clifford Wolf	b0c0ede879	Added "init" attribute support to verilog backend	2015-04-04 18:06:52 +02:00
Clifford Wolf	67e6dcd34a	Added Verilog backend $dffsr support	2015-03-18 08:01:37 +01:00
Clifford Wolf	756b4064b2	Fixed "write_verilog -attr2comment" handling of "*/" in strings	2015-02-13 22:48:10 +01:00
Clifford Wolf	43951099cf	Added dict/pool.sort()	2015-01-24 00:13:27 +01:00
Clifford Wolf	146f769bee	Cosmetic changes in verilog output format	2015-01-02 22:57:08 +01:00
Clifford Wolf	9e6fb0b02c	Replaced std::unordered_map as implementation for Yosys::dict	2014-12-26 21:35:22 +01:00
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00
Clifford Wolf	5df192e71c	Added $dffe support to write_verilog	2014-12-20 00:03:20 +01:00
Clifford Wolf	461594bb83	Fixed generation of temp names in verilog backend	2014-11-07 14:40:06 +01:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	b9cb483f3e	Using $pos models for $bu0	2014-09-03 21:20:59 +02:00
Clifford Wolf	5dce303a2a	Changed backend-api from FILE to std::ostream	2014-08-23 13:54:21 +02:00
Clifford Wolf	f82c978e08	Fixed AOI/OAI expr handling in verilog backend	2014-08-16 22:05:09 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	88cf00ce78	Be more conservative with printing decimal numbers in verilog backend	2014-08-02 21:54:02 +02:00
Clifford Wolf	ca1b5d50e0	Improved verilog output for ordinary $mux cells	2014-08-02 21:10:08 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	5826670009	Various RTLIL::SigSpec related code cleanups	2014-07-25 14:25:42 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	a30e2857c7	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend	2014-07-20 02:16:30 +02:00
Clifford Wolf	0c67393313	Added support for $bu0 to verilog backend	2014-07-20 01:56:16 +02:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00