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5160 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf
ddd31a0b66 Small improvements in PerformanceTimer API 2014-07-27 15:14:02 +02:00
Clifford Wolf
77a1462f2d Fixed bug in opt_clean 2014-07-27 15:13:29 +02:00
Clifford Wolf
d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf
4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs 2014-07-27 14:47:48 +02:00
Clifford Wolf
cbc3a46a97 Added RTLIL::SigSpecConstIterator 2014-07-27 14:47:23 +02:00
Clifford Wolf
dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups 2014-07-27 13:19:05 +02:00
Clifford Wolf
d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf
7661ded8dd Fixed verific bindings for new RTLIL api 2014-07-27 12:00:28 +02:00
Clifford Wolf
6b34215efd Fixed ilang parser for new RTLIL API 2014-07-27 11:56:35 +02:00
Clifford Wolf
49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf
675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf
0bd8fafbd2 Added RTLIL::Design::modules() 2014-07-27 11:18:30 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
d088854b47 Added conversion from ObjRange to std::vector and std::set 2014-07-27 11:18:30 +02:00
Clifford Wolf
1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange 2014-07-27 11:18:30 +02:00
Clifford Wolf
ddc5b41848 Using std::move() in SigSpec move constructor 2014-07-27 09:20:59 +02:00
Clifford Wolf
7f3dc86ecd Added RTLIL::SigSpec move constructor and move assignment operator 2014-07-27 02:11:57 +02:00
Clifford Wolf
c91570bde3 Mostly cosmetic changes to rtlil.h 2014-07-27 02:00:04 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
d7916a49af New message for completion of build 2014-07-26 21:35:16 +02:00
Clifford Wolf
d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf
946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf
d49dec1f86 Added tests/various/.gitignore 2014-07-26 17:43:41 +02:00
Clifford Wolf
b21ebe1859 Added tests/various/submod_extract.ys 2014-07-26 17:22:18 +02:00
Clifford Wolf
267c615640 Added support for here documents 2014-07-26 17:21:40 +02:00
Clifford Wolf
3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf
97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf
a84cb04935 Merge automatic and manual code changes for new cell connections API 2014-07-26 16:00:30 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cd6574ecf6 Added some missing "const" in rtlil.h 2014-07-26 15:58:22 +02:00
Clifford Wolf
7ac9dc7f6e Added RTLIL::Module::connections() 2014-07-26 15:58:21 +02:00
Clifford Wolf
b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) 2014-07-26 14:31:47 +02:00
Clifford Wolf
027819c7e8 Use "wget -N" in tests/vloghtb/run-test.sh 2014-07-26 14:08:43 +02:00
Clifford Wolf
b90f443338 Added "passed" message to make test targets 2014-07-26 14:08:20 +02:00
Clifford Wolf
3719281ed4 Automatically pack SigSpec on copy/assign 2014-07-26 13:59:30 +02:00
Clifford Wolf
e75e495c2b Added new RTLIL::Cell port access methods 2014-07-26 12:22:58 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
665759fcee Cosmetic fixes for "make abc" 2014-07-26 11:55:58 +02:00
Clifford Wolf
f8a68b8f55 Added "Checklist for adding internal cell types" 2014-07-26 11:23:43 +02:00
Clifford Wolf
4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf
5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf
c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API 2014-07-25 14:23:10 +02:00
Clifford Wolf
1834af5e53 Added "make vgtest" 2014-07-25 13:24:26 +02:00
Clifford Wolf
309d64d46a Fixed two memory leaks in ast simplify 2014-07-25 13:24:10 +02:00
Clifford Wolf
50f22ff30c Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
Clifford Wolf
0520bfea89 Fixed memory corruption in "opt_reduce" pass 2014-07-25 12:49:51 +02:00