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Author SHA1 Message Date
Eddie Hung
151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Eddie Hung
a37574ccbf Fix muxAB logic 2019-07-23 14:52:14 -07:00
Eddie Hung
0dd2a125f6 Remove debug print 2019-07-23 14:21:45 -07:00
Eddie Hung
dc0c853abe Simplify and fix for MACs 2019-07-23 14:20:34 -07:00
Eddie Hung
4f11ff8ebd Fix typo 2019-07-23 13:58:56 -07:00
Dan Ravensloft
67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung
a66f17b6a7
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp 
ice40: Fix SB_MAC16 sim model for signed modes
 2019-07-23 09:56:58 -07:00
Eddie Hung
33c984a044 Fix spacing 2019-07-22 16:37:13 -07:00
Eddie Hung
cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung
068617f094 Pack hi and lo registers separately 2019-07-22 16:12:57 -07:00
Eddie Hung
8c31441ba0 SigSpec::extract() to return as many bits as poss if out of bounds 2019-07-22 16:10:21 -07:00
Eddie Hung
4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung
304cefbbe2 Pack Y register 2019-07-22 15:05:16 -07:00
Eddie Hung
5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung
5a14b6e1f6 Pack adders not just accumulators 2019-07-22 13:01:49 -07:00
Eddie Hung
3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung
280288a62a Update changelog 2019-07-22 07:46:06 -07:00
Eddie Hung
be3d9c8eaa
Merge pull request #1214 from jakobwenzel/astmod_clone 
initialize noblackbox and nowb in AstModule::clone
 2019-07-22 07:42:53 -07:00
Jakob Wenzel
e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
Clifford Wolf
c6d8692c97 Add "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-20 15:06:28 +02:00
Eddie Hung
e0720a8018 Restore old ffY behaviour 2019-07-19 22:47:08 -07:00
Eddie Hung
f9d08a5e5e Cleanup 2019-07-19 20:25:28 -07:00
Eddie Hung
47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung
595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung
09beeee38a Try and fix again 2019-07-19 14:40:57 -07:00
Eddie Hung
e87916b7eb Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp 2019-07-19 14:03:34 -07:00
Eddie Hung
c926eeb43a Add another test 2019-07-19 14:02:46 -07:00
Eddie Hung
cb0fd05215 Do not access beyond bounds 2019-07-19 13:58:50 -07:00
Eddie Hung
54708dfbd7 Add an SigSpec::at(offset, defval) convenience method 2019-07-19 13:54:57 -07:00
Eddie Hung
3a87dc3524 Wrap A and B in sigmap 2019-07-19 13:23:07 -07:00
Eddie Hung
31b0002e8c Remove "top" from message 2019-07-19 13:20:45 -07:00
Eddie Hung
8791e0caac Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp 2019-07-19 13:18:20 -07:00
Eddie Hung
bcd8027182 Also optimise MSB of $sub 2019-07-19 13:11:48 -07:00
Eddie Hung
5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung
fc0e36d1c0 wreduce for $sub 2019-07-19 12:50:21 -07:00
Eddie Hung
4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung
25ff27e37f SigSpec::extract to take negative lengths 2019-07-19 12:34:04 -07:00
Eddie Hung
bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung
3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung
1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung
9ad11ea2cc Fine tune ice40_dsp.pmg, add support for packing subsets of registers 2019-07-19 10:57:32 -07:00
Eddie Hung
8f0e796be1 Add support for ice40 signed multipliers 2019-07-19 10:38:13 -07:00
Eddie Hung
7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung
ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung
d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
Eddie Hung
2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00