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Code Activity
6210 commits 122 branches 59 tags 73 MiB
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613 commits

Author SHA1 Message Date
Eddie Hung
c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
whitequark
ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Eddie Hung
c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung
b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung
3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
Gabriel L. Somlo
8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung
4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung
a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung
137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
c226af3f56 Fix spacing 2019-06-26 20:03:34 -07:00
Eddie Hung
26efd6f0a9 Support more than one port in the abc_scc_break attr 2019-06-26 19:57:54 -07:00
Eddie Hung
d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung
a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung
5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung
babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung
49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung
1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung
ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Clifford Wolf
ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 19:24:41 +02:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf
9286b6f013 Add "muxcover -freedecode" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 10:02:10 +02:00
Eddie Hung
54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Clifford Wolf
891ea6512e Improvements in muxcover 
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
 2019-06-20 19:47:59 -07:00
Clifford Wolf
40188457d1 Add support for partial matches to muxcover, fixes #1091 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 19:47:59 -07:00
Eddie Hung
0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung
3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Clifford Wolf
06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Eddie Hung
96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Eddie Hung
4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung
63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung
b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung
7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung
2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah
9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Eddie Hung
2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung
b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00