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292 commits

Author SHA1 Message Date
clairexen
1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Xiretza
928fd40c2e Respect \A_SIGNED for $shift 
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
 2020-08-18 19:36:24 +02:00
Marcelina Kościelnicka
9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka
817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Marcelina Kościelnicka
832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
b0bee396a8 Add new builtin FF types 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
 2020-06-23 15:40:02 +02:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Claire Wolf
3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung
d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Xiretza
edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Marcelina Kościelnicka
aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung
67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Eddie Hung
13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung
97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung
e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung
57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung
722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Eddie Hung
004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Marcelina Kościelnicka
53ba3cf718 Fix the truth table for $_SR_* cells. 
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
 2020-04-15 17:17:48 +02:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung
7b38cde2df cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
Eddie Hung
7b09a20c0c cmp2lcu: fail if `LUT_WIDTH < 2 2020-04-03 14:28:22 -07:00
Eddie Hung
34c9b83854 synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
Eddie Hung
5b87720b16 synth: use +/cmp2lcu.v in generic 'synth' too 2020-04-03 14:28:22 -07:00
Eddie Hung
2bf03c6ae0 Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
Eddie Hung
99a32432aa +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc Refactor +/cmp2lcu.v into recursive techmap 2020-04-03 14:28:22 -07:00
Eddie Hung
8e851badc4 Cleanup 2020-04-03 14:28:22 -07:00
Eddie Hung
da880d5016 Cleanup cmp2lcu.v 2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678 techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
Eddie Hung
fffe42d4c1 cmp2lut: comment out unused since 362f4f9 2020-04-03 14:28:04 -07:00
Marcin Kościelnicki
0ed1062557 simcells.v: Generate the fine FF cell types by a python script. 
This makes adding more FF types in the future much more manageable.

Fixes #1824.
 2020-04-02 18:37:15 +02:00
Miodrag Milanovic
acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
N. Engelhardt
0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc 
Add -flowmap option to `synth{,_ice40}`
 2020-03-03 19:15:41 +01:00
Dan Ravensloft
d7987fec12 Add -flowmap to synth and synth_ice40 2020-02-28 14:29:57 +00:00
Eddie Hung
ac24a23e31 Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
Eddie Hung
affae35847 techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
Eddie Hung
4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung
72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung
152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung
5a63c19747 abc9_ops: -write_box is empty, output a dummy box to prevent ABC error 2020-01-15 13:14:48 -08:00
Clifford Wolf
362f4f996d Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-11 15:07:29 +01:00