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7048 commits 122 branches 59 tags 73 MiB
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Author SHA1 Message Date
Eddie Hung
af840bbc63 Move neg-pol to pos-pol mapping from ff_map to cells_map.v 2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033 Fix spacing 2019-04-26 19:46:34 -07:00
Eddie Hung
0f1ba94924 Remove split_shiftx tests 2019-04-26 19:45:47 -07:00
Eddie Hung
d855683917 Revert synth_xilinx 'fine' label more to how it used to be... 2019-04-26 16:53:16 -07:00
Eddie Hung
ccc283737d Apparently, this reduces number of MUXCY/XORCY 2019-04-26 16:28:48 -07:00
Eddie Hung
e31e21766d Try a different approach with 'muxcover' 2019-04-26 16:09:54 -07:00
Eddie Hung
76b7c5d4cc Merge remote-tracking branch 'origin/master' into xc7mux 2019-04-26 15:35:55 -07:00
Eddie Hung
ea0e0722bb Where did this check come from!?! 2019-04-26 15:35:34 -07:00
Eddie Hung
6b9ca7cd6d Remove split_shiftx call 2019-04-26 15:32:58 -07:00
Eddie Hung
dcc8a13e48 Revert "Merge branch 'eddie/split_shiftx' into xc7mux" 
This reverts commit 3042d58330, reversing
changes made to feff976454.
 2019-04-26 15:32:02 -07:00
Eddie Hung
8469d9fe9f Missing newline 2019-04-26 14:51:37 -07:00
Eddie Hung
727eec04c5 Refactor synth_xilinx to auto-generate doc 2019-04-26 14:32:18 -07:00
Eddie Hung
1ea6d7920f Cleanup ice40 2019-04-26 14:31:59 -07:00
Eddie Hung
159e7cc298 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
Eddie Hung
4473fd1502 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:14:33 -07:00
Eddie Hung
976d8030dc Actually use pm.st.shiftxB 2019-04-25 19:59:33 -07:00
Eddie Hung
f14d7f0df6 Cleanup superseded 2019-04-25 19:43:41 -07:00
Eddie Hung
019c48b508 bitblast_shiftx -> split_shiftx 2019-04-25 19:38:35 -07:00
Eddie Hung
fb4348f840 Fix for when B_WIDTH has trailing zeroes 2019-04-25 19:38:19 -07:00
Eddie Hung
880652283c Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux 2019-04-25 18:52:20 -07:00
Eddie Hung
ece2c49e92 In order to indicate a failed pattern, blacklist? 2019-04-25 18:39:13 -07:00
Eddie Hung
0eb7150a57 Add test 2019-04-25 18:08:05 -07:00
Eddie Hung
af3c374a35 Elaborate on help message 2019-04-25 17:35:39 -07:00
Eddie Hung
3042d58330 Merge branch 'eddie/split_shiftx' into xc7mux 2019-04-25 17:31:27 -07:00
Eddie Hung
ccd0729456 Add split_shiftx command 2019-04-25 17:23:59 -07:00
Eddie Hung
8d00b9ef7e Make pmgen support files more generic 2019-04-25 17:23:46 -07:00
Eddie Hung
feff976454 synth_xilinx to call bitblast_shiftx 2019-04-25 17:11:18 -07:00
Eddie Hung
408161ea3a
Misspelling 2019-04-25 16:46:13 -07:00
Eddie Hung
eec314e262 Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
Eddie Hung
f96d82a5f1 Add -nocarry option to synth_xilinx 2019-04-24 16:46:41 -07:00
Eddie Hung
ac2aff9e28 Fix abc9 with (* keep *) wires 2019-04-23 16:11:39 -07:00
Eddie Hung
bfd71e0990 Fix abc9 with (* keep *) wires 2019-04-23 16:11:14 -07:00
Eddie Hung
9d122d3c51 Refactor into AigerReader::post_process() 2019-04-23 15:06:19 -07:00
Clifford Wolf
67005633e2 Add specify support to README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 23:01:38 +02:00
Clifford Wolf
64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Eddie Hung
d9c915042a Move clean from aigerparse to abc9 2019-04-23 13:42:35 -07:00
Eddie Hung
91c3afcab7 Use nonblocking 2019-04-23 13:42:06 -07:00
Clifford Wolf
4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
634482380c Preserve $specify[23] cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088 Allow $specify[23] cells in blackbox modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
846eb5ea98 Add $specify2/$specify3 support to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
0bf9d0087c Add support for $assert/$assume/$cover to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
aec2475a9d Add CellTypes support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
e1d73e03d3 Add InternalCellChecker support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf Checking and fixing specify cells in genRTLIL 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b Un-break default specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd Add $specify2 and $specify3 cells to simlib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00