26 commits

Author	SHA1	Message	Date
Emil Jiří Tywoniak	6527cc2134	gowin: fix test	2025-09-23 20:03:50 +02:00
Robert O'Callahan	8b75c06141	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
Lofty	7ae4041e20	ice40, ecp5, gowin: enable ABC9 by default	2023-11-13 15:28:13 +00:00
Ralf Fuest	30f1d10948	gowin: Fix X output of $alu techmap	2023-05-01 17:56:41 +02:00
Marcelina Kościelnicka	f61f2a4078	gowin: Fix LUT RAM inference, add more models.	2022-02-09 09:04:34 +01:00
Pepijn de Vos	c2d358484f	Gowin: deal with active-low tristate (#2971) ... * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests	2021-08-20 21:21:06 +02:00
Xiretza	acd47bbd52	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
Marcelina Kościelnicka	9a4f420b4b	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka	c73ebeb90e	gowin: Use dfflegalize.	2020-07-06 12:27:46 +02:00
Dan Ravensloft	7f45cab27a	synth_gowin: ABC9 support ... This adds ABC9 support for synth_gowin; drastically improving synthesis quality.	2020-07-05 22:07:17 +02:00
Marcelina Kościelnicka	34d2fbd2f9	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
Eddie Hung	c082329af3	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
Eddie Hung	caab66111e	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
Pepijn de Vos	a7d34a7cb5	update test	2019-12-03 16:56:15 +01:00
Pepijn de Vos	a3b25b4af8	Use -match-init to not synth contradicting init values	2019-12-03 15:12:25 +01:00
Pepijn de Vos	72d03dc910	attempt to fix formatting	2019-11-25 14:50:34 +01:00
Pepijn de Vos	6c79abbf5a	gowin: add and test dff init values	2019-11-25 14:33:21 +01:00
Marcin Kościelnicki	e110df9c48	gowin: Remove show command from tests.	2019-11-22 14:49:35 +01:00
Pepijn de Vos	ab8c521030	fix fsm test with proper clock enable polarity	2019-11-11 17:51:26 +01:00
Pepijn de Vos	0e5dbc4abc	fix wide luts	2019-11-06 19:48:18 +01:00
Pepijn de Vos	df8390f5df	don't cound exact luts in big muxes; futile and fragile	2019-10-30 14:58:25 +01:00
Pepijn de Vos	903f997391	add tristate buffer and test	2019-10-28 15:18:01 +01:00
Pepijn de Vos	9517525224	do not use wide luts in testcase	2019-10-28 14:40:12 +01:00
Pepijn de Vos	8226f2db0b	ALU sim tweaks	2019-10-24 13:39:43 +02:00
Pepijn de Vos	83fbfe0964	Add some tests ... Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram	2019-10-21 16:25:15 +02:00