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5983 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
81bb952e5d Handle "always 1" like "always -1" in .smtc files 2017-01-02 20:08:03 +01:00
Andrew Zonenberg
babd8dc5b1 Merge https://github.com/cliffordwolf/yosys 2017-01-01 14:08:16 -08:00
Clifford Wolf
f0df7dd796 Added cell port resizing to hierarchy pass 2017-01-01 23:03:44 +01:00
Andrew Zonenberg
27a626ce98 greenpak4: Added POUT to GP_COUNTx cells 2017-01-01 00:56:20 -08:00
Clifford Wolf
a7fb64efe6 Updated ABC to hg id 55cd83f432c0 2016-12-31 21:52:27 +01:00
Clifford Wolf
6b2c23c721 Bugfix in RTLIL::SigSpec::remove2() 2016-12-31 16:14:42 +01:00
Clifford Wolf
7da7a6d1df Updated ABC to hg id 8c6a635f7a20 2016-12-29 12:20:35 +01:00
Clifford Wolf
2198948398 Improved write_json help message 2016-12-29 12:13:29 +01:00
Clifford Wolf
4f5efc3416 Updated ABC to hg id f591c081d5e7 2016-12-26 17:52:38 +01:00
Clifford Wolf
4cf3170194 Merge pull request #284 from azonenberg/master 
greenpak4: Support for many new cell types
 2016-12-24 14:28:39 +01:00
Andrew Zonenberg
5ffede5c0e Merge pull request #1 from azonenberg-hk/master 
Pull changes from HK trip
 2016-12-23 12:32:55 -08:00
Andrew Zonenberg
9f69a70d74 Merge https://github.com/cliffordwolf/yosys 2016-12-23 05:10:37 -08:00
Clifford Wolf
33a22f8768 Simplified log_spacer() code 2016-12-23 02:06:46 +01:00
Clifford Wolf
a0dff87a57 Added "yosys -W regex" 2016-12-22 23:41:44 +01:00
Clifford Wolf
f144adec58 Added AIGER back-end to automatic back-end detection 2016-12-21 10:16:47 +01:00
Clifford Wolf
f31e6a7174 Updated ABC to hg rev a4872e22c646 2016-12-21 10:16:10 +01:00
Clifford Wolf
3d0e51f813 Updated ABC to hg rev 8bab2eedbba4 2016-12-21 09:13:20 +01:00
Andrew Zonenberg
ada98844b9 greenpak4: Added INT pin to GP_SPI 2016-12-21 11:35:29 +08:00
Andrew Zonenberg
6b526e9382 greenpak4: removed unused MISO pin from GP_SPI 2016-12-21 11:33:32 +08:00
Andrew Zonenberg
638f3e3b12 greenpak4: Removed SPI_BUFFER parameter 2016-12-20 13:07:49 +08:00
Andrew Zonenberg
073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin 2016-12-20 12:34:56 +08:00
Andrew Zonenberg
d4a05b499e greenpak4: Changed port names on GP_SPI for clarity 2016-12-20 10:30:38 +08:00
Andrew Zonenberg
eb80ec84aa greenpak4: Initial implementation of GP_SPI cell 2016-12-20 09:58:02 +08:00
Andrew Zonenberg
fcd40fd41e Merge https://github.com/cliffordwolf/yosys 2016-12-17 12:02:46 +08:00
Andrew Zonenberg
de1d81511a greenpak4: Updated GP_DCMP cell model 2016-12-17 12:01:22 +08:00
Andrew Zonenberg
7cdba8432c greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF. 2016-12-16 15:14:20 +08:00
Clifford Wolf
3886669ab6 Added "verilog_defines" command 2016-12-15 17:49:28 +01:00
Andrew Zonenberg
bea6e2f11f greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX 2016-12-15 15:19:35 +08:00
Andrew Zonenberg
3690aa556c greenpak4: More fixups of GP_DCMPx cells 2016-12-15 07:19:08 +08:00
Andrew Zonenberg
3491d33863 greenpak4: And another typo :( 2016-12-15 07:17:07 +08:00
Andrew Zonenberg
ea787e6be3 greenpak4: Fixed another typo 2016-12-15 07:16:26 +08:00
Andrew Zonenberg
58da621ac3 greenpak4: Fixed typo 2016-12-15 07:15:38 +08:00
Andrew Zonenberg
262f8f913c greenpak4: Cleaned up trailing spaces in cells_sim 2016-12-14 14:14:45 +08:00
Andrew Zonenberg
c77e6e6114 greenpak4: Added GP_DCMPREF / GP_DCMPMUX 2016-12-14 14:14:26 +08:00
Clifford Wolf
00761de1b7 Bugfix in comment handling 2016-12-13 13:48:09 +01:00
Andrew Zonenberg
01d8278e53 Merge https://github.com/cliffordwolf/yosys 2016-12-12 17:05:06 +08:00
Clifford Wolf
a61c88f122 Added $anyconst support to AIGER back-end 2016-12-11 13:48:18 +01:00
Clifford Wolf
8a717ae1dc Merge branch 'LSS-USP-unit-test-structure' 2016-12-11 11:03:25 +01:00
Clifford Wolf
71c47f13ed Some minor CodingReadme changes in unit test section 2016-12-11 11:02:56 +01:00
Clifford Wolf
5c96982522 Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
Andrew Zonenberg
c3c2983d12 Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF 2016-12-11 10:04:00 +08:00
rodrigosiqueira
b932e2355d Improved unit test structure 
Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>

* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
 2016-12-10 18:21:56 -02:00
Andrew Zonenberg
8f3d1f8fcf greenpak4: Added support for inferred input/output inverters on latches 2016-12-10 19:58:32 +08:00
Andrew Zonenberg
c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
Andrew Zonenberg
797c03997e greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency 2016-12-10 13:57:37 +08:00
Andrew Zonenberg
8767cdcac9 Added GP_DLATCH and GP_DLATCHI 2016-12-05 23:49:06 -08:00
Andrew Zonenberg
981f014301 Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet. 2016-12-05 21:22:41 -08:00
Andrew Zonenberg
e6ab00d419 Updated help text for synth_greenpak4 2016-12-05 20:11:37 -08:00
rodrigosiqueira
3f2f64f414 Added explanation about configure and create test 
Added explanation about configure unit test environment and how to add new unit tests
 2016-12-04 11:35:13 -02:00
rodrigosiqueira
e0152319f5 Added required structure to implement unit tests 
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.

Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
 2016-12-04 11:34:27 -02:00