mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-26 13:06:12 +00:00
Code Activity
591 commits 109 branches 57 tags 56 MiB
Commit graph

3 commits

Author SHA1 Message Date
Clifford Wolf
63285b300c Renamed temp module generated by "abc" pass from "logic" to "netlist" 2013-11-19 01:03:57 +01:00
Clifford Wolf
a694324a75 Fixed abc pass blif parser for constant bits 2013-11-13 15:46:28 +01:00
Clifford Wolf
ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00