Stefan Biereigel
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816082d5a1
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Merge branch 'master' into wandwor
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2019-05-27 19:07:46 +02:00 |
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Stefan Biereigel
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cd12f2ddcf
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remove leftovers from ast data structures
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2019-05-27 18:01:44 +02:00 |
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Stefan Biereigel
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ed625a3102
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move wand/wor resolution into hierarchy pass
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2019-05-27 18:00:22 +02:00 |
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Clifford Wolf
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92dde319fc
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Merge pull request #1044 from mmicko/invalid_width_range
Give error instead of asserting for invalid range, fixes #947
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2019-05-27 13:26:12 +02:00 |
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Miodrag Milanovic
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84ffb21708
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Give error instead of asserting for invalid range, fixes #947
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2019-05-27 12:25:18 +02:00 |
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Miodrag Milanovic
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34417ce55f
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Added support for unsized constants, fixes #1022
Includes work from @sumit0190 and @AaronKel
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2019-05-27 11:42:10 +02:00 |
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Stefan Biereigel
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85de9d26c1
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fix assignment of non-wires
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2019-05-23 17:55:56 +02:00 |
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Stefan Biereigel
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fd003e0e97
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fix indentation across files
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2019-05-23 13:57:27 +02:00 |
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Stefan Biereigel
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075a48d3fa
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implementation for assignments working
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2019-05-23 13:57:27 +02:00 |
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Stefan Biereigel
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9df04d7e75
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make lexer/parser aware of wand/wor net types
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2019-05-23 13:57:27 +02:00 |
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Clifford Wolf
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752553d8e9
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Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
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2019-05-06 20:57:15 +02:00 |
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Clifford Wolf
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d187be39d6
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
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2019-05-06 15:41:13 +02:00 |
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Clifford Wolf
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87426f5a06
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Improve write_verilog specify support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-04 08:46:24 +02:00 |
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Eddie Hung
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d9c4644e88
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Merge remote-tracking branch 'origin/master' into clifford/specify
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2019-05-03 15:05:57 -07:00 |
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Clifford Wolf
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6bbe2fdbf3
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Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 10:01:54 +02:00 |
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Clifford Wolf
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3b6a02d3a7
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Fix width detection of memory access with bit slice, fixes #974
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:57:26 +02:00 |
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Clifford Wolf
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59d74a3348
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Re-enable "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:02:39 +02:00 |
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Clifford Wolf
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e35fe1344d
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Disabled "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 20:22:50 +02:00 |
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Clifford Wolf
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9af825e31e
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Add final loop variable assignment when unrolling for-loops, fixes #968
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 15:03:32 +02:00 |
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Clifford Wolf
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71c38d9de5
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Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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012c6af088
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Allow $specify[23] cells in blackbox modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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b232e027bf
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Checking and fixing specify cells in genRTLIL
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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4ad0ea5c3c
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Determine correct signedness and expression width in for loop unrolling, fixes #370
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-22 18:19:02 +02:00 |
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Clifford Wolf
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b40af877f3
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Merge pull request #909 from zachjs/master
support repeat loops with constant repeat counts outside of constant functions
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2019-04-22 08:51:34 +02:00 |
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Clifford Wolf
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5b7fea5245
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Add "noblackbox" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-21 11:40:09 +02:00 |
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Clifford Wolf
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fb7f02be55
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New behavior for front-end handling of whiteboxes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-20 22:24:50 +02:00 |
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Clifford Wolf
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f4abc21d8a
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Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-18 17:45:47 +02:00 |
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Zachary Snow
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5855024ccc
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support repeat loops with constant repeat counts outside of constant functions
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2019-04-09 12:28:32 -04:00 |
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Clifford Wolf
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638be461c3
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Fix mem2reg handling of memories with upto data ports, fixes #888
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 22:21:17 +01:00 |
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Clifford Wolf
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da42f10765
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Improve "read_verilog -dump_vlog[12]" handling of upto ranges
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 22:20:16 +01:00 |
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Clifford Wolf
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9b0e7af6d7
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Improve read_verilog debug output capabilities
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-21 20:52:29 +01:00 |
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Zachary Snow
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a5f4b83637
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fix local name resolution in prefix constructs
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2019-03-18 20:43:20 -04:00 |
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Clifford Wolf
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17caaa3fa8
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Improve handling of "full_case" attributes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 17:51:21 +01:00 |
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Clifford Wolf
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d25a0c8ade
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Improve handling of memories used in mem index expressions on LHS of an assignment
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:12:02 +01:00 |
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Clifford Wolf
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a4ddc569b4
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Remove outdated "blocking assignment to memory" warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:10:55 +01:00 |
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Clifford Wolf
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ab5b50ae3c
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Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:09:47 +01:00 |
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Clifford Wolf
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cebd21aa96
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Merge pull request #858 from YosysHQ/clifford/svalabels
Add support for using SVA labels in yosys-smtbmc console output
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2019-03-09 11:14:57 -08:00 |
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Clifford Wolf
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a330c68363
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Fix handling of task output ports in clocked always blocks, fixes #857
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-07 22:44:37 -08:00 |
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Clifford Wolf
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22ff60850e
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Add support for SVA labels in read_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-07 11:17:32 -08:00 |
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Clifford Wolf
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52f80718a7
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Merge pull request #848 from YosysHQ/clifford/fix763
Fix error for wire decl in always block, fixes 763
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2019-03-02 16:32:58 -08:00 |
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Clifford Wolf
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ae9286386d
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Only run derive on blackbox modules when ports have dynamic size
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 12:36:46 -08:00 |
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Clifford Wolf
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3a51714451
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Fix error for wire decl in always block, fixes #763
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 11:56:44 -08:00 |
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Clifford Wolf
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ce6695e22c
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Fix $global_clock handling vs autowire
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 10:38:13 -08:00 |
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Clifford Wolf
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5d93dcce86
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Fix $readmem[hb] for mem2reg memories, fixes #785
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-02 09:58:20 -08:00 |
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Clifford Wolf
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7cfae2c52f
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Use mem2reg on memories that only have constant-index write ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-01 13:35:09 -08:00 |
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Clifford Wolf
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1816fe06af
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Fix handling of defparam for when default_nettype is none
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-24 20:09:41 +01:00 |
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Clifford Wolf
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23148ffae1
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Fixes related to handling of autowires and upto-ranges, fixes #814
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 18:40:11 +01:00 |
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Clifford Wolf
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974927adcf
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Fix handling of expression width in $past, fixes #810
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 17:55:33 +01:00 |
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Clifford Wolf
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28fba903c5
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Fix segfault in printing of some internal error messages
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-21 17:40:52 +01:00 |
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Clifford Wolf
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807b3c7697
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Fix sign handling of real constants
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-02-13 12:36:47 +01:00 |
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