mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-21 02:30:25 +00:00
Code Activity
15522 commits 117 branches 57 tags 55 MiB
Commit graph

1 commit

Author SHA1 Message Date
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00