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4 commits

Author SHA1 Message Date
Gary Wong
9f022f01da verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-08-08 15:36:43 +02:00
Emil J. Tywoniak
5ae0120134 Revert "verilog: add support for SystemVerilog string literals." 
This reverts commit 5feb1a1752.
 2025-08-08 15:35:08 +02:00
Krystine Sherwin
3959d19291
Reapply "Add groups to command reference" 
This reverts commit 81f87ce6ed.
 2025-08-06 13:52:12 +12:00
Krystine Sherwin
385d58562d
Docs: Move verilog.rst to using_yosys 
Was previously in yosys_internals which is more developer focused, rather than user focused.
 2025-08-05 09:53:58 +12:00
Renamed from docs/source/yosys_internals/verilog.rst (Browse further)