3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-22 15:34:36 +00:00
Commit graph

8 commits

Author SHA1 Message Date
Lofty
9cfa5fb369 analogdevices: prepare for t40lp timings 2025-10-16 08:43:08 +01:00
Krystine Sherwin
151f530677 analogdevices: Adding RBRAM2 and -tech 2025-10-16 08:43:08 +01:00
Krystine Sherwin
edeb6128ab analogdevices: (some) Native BRAM
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
2025-10-16 08:43:08 +01:00
Lofty
b3e3614c96 analogdevices: LUTRAM config 2025-10-16 08:43:08 +01:00
Lofty
0bec90930f analogdevices: update timing model 2025-10-16 08:43:08 +01:00
Lofty
2cdd97a8d4 test suite 2025-10-16 08:43:08 +01:00
Lofty
04fd4d4601 synth_analogdevices: remove scopeinfo cells 2025-10-16 08:43:08 +01:00
Lofty
7878a7e2bd Create synth_analogdevices 2025-10-16 08:43:08 +01:00