yosys

15764 commits 121 branches 59 tags 69 MiB

Author	SHA1	Message	Date
Eddie Hung	de79978372	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325 ) * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled	2020-09-23 09:15:24 -07:00
Marcin Kościelnicki	7b350cacd4	xilinx: Support multiplier mapping for all families. This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.	2019-10-22 18:06:57 +02:00

Author

SHA1

Message

Date

Eddie Hung

de79978372

xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325 )

* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

2020-09-23 09:15:24 -07:00

Marcin Kościelnicki

7b350cacd4

xilinx: Support multiplier mapping for all families.

This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.

2019-10-22 18:06:57 +02:00

Renamed from techlibs/xilinx/dsp_map.v (Browse further)

2 commits