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2 commits

Author SHA1 Message Date
Richard Herveille
2fde482629 Fixed data/address width parameters 2024-03-06 02:45:07 +01:00
Dan Ravensloft
67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Renamed from techlibs/intel/common/brams_map.v (Browse further)