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Code Activity
12690 commits 122 branches 59 tags 73 MiB
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423 commits

Author SHA1 Message Date
phsauter
9ca57d9f13 peepopt: fix and refactor shiftadd 
- moved all selection and filtering logic to the match block
- applied less-verbose code suggestions
- removed constraint on number of bits in shift-amount
- added check for possible wrap-arround in the operation
 2023-11-06 14:01:37 +01:00
Philippe Sauter
72c6a01e67 peepopt: Add initial shiftadd pattern 2023-11-06 14:01:37 +01:00
Martin Povišer
d6d1cc705e pmgen: Fix sample syntax 2023-10-16 14:19:15 +02:00
Martin Povišer
660be4a31e peepopt: Describe rules in help message 2023-10-16 14:19:15 +02:00
Martin Povišer
5c0c8251c3 peepopt: Remove broken -generate option 2023-10-16 14:19:10 +02:00
Martin Povišer
aa9b86aeec peepopt: Add left-shift 'shiftmul' variant 
Add a separate shiftmul pattern to match on left shifts which implement
demuxing. This mirrors the right shift pattern matcher but is probably
best kept separate instead of merging the two into a single matcher.
In any case the diff of the two matchers should be easily readable.
 2023-10-16 13:52:38 +02:00
Martin Povišer
038a5e1ed4 peepopt: Support shift amounts zero-padded from below 
The `opt_expr` pass running before `peepopt` can interfere with the
detection of a shiftmul pattern due to some of the bottom bits of the
shift amount being replaced with constant zero. Extend the detection to
cover those situations as well.
 2023-10-16 13:52:06 +02:00
Martin Povišer
dd1a8ae49a peepopt: Try to use original wires 2023-10-16 13:52:06 +02:00
Martin Povišer
bd8a81a907 peepopt: Clean up 'shiftmul' a bit 
No functional change intended.
 2023-10-16 13:52:06 +02:00
Martin Povišer
a0c3be3aae peepopt: Drop unused 'initbits' code 
Drop code that was once used by the 'dffmux' pattern but now is unused
after that pattern has been obsoleted by the 'opt_dff' pass.
 2023-10-16 13:52:06 +02:00
KrystalDelusion
9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Scott Thibault
0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault
e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic
d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic
cbb6887ac8 Correct way of setting maybe_unsused on labels 2021-11-05 10:36:15 +01:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Miodrag Milanovic
81c2b92bb4 Add _pm.h files to GENLIST, fixes vcxsrc target 2021-03-11 15:56:32 +01:00
Larry Doolittle
84c0b5c690 passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings 
Verified that the result still builds and passes self-tests
 2020-12-23 14:38:25 -08:00
Miodrag Milanovic
82dcf78cd9 Return nice error in pmgen generated code, fixes #2482 2020-12-09 11:06:22 +01:00
clairexen
799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 
peeopt.shiftmul: Add a signedness check.
 2020-08-20 16:23:07 +02:00
clairexen
6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
Marcelina Kościelnicka
a0e99a9f3f peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
c1ed1c28be peeopt.shiftmul: Add a signedness check. 
Fixes #2332.
 2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka
e89cc9c02f peepopt.muldiv: Add a signedness check. 
Fixes #2318.
 2020-08-04 16:30:24 +02:00
Marcelina Kościelnicka
cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00
whitequark
c8c3c7af87 Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused). 
[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
 2020-06-19 15:48:58 +00:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Eddie Hung
592baebd22 xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
Eddie Hung
7f33a0294b Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 
synth_xilinx: add -dsp-multonly
 2020-02-02 14:53:32 +00:00
David Shah
65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Eddie Hung
e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e xilinx_dsp: add parameter defaults 2020-01-17 16:05:10 -08:00
Eddie Hung
4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Miodrag Milanovic
3e14ff1667 fixed invalid char 2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
e226a8f7f1 Minor nit fixes 2019-12-25 15:39:40 +01:00
Eddie Hung
1d0ac659ad Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too 2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5 Fix CEA/CEB check 2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377 Fix checking CE[AB] and for direct connections 2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309 Support unregistered cascades for A and B inputs 2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8 Add DSP48A* PCOUT -> PCIN cascade support 2019-12-23 11:42:46 -08:00
Marcin Kościelnicki
666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00