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Author	SHA1	Message	Date
Clifford Wolf	a3ac6b6f47	Progress on presentation	2014-01-27 20:42:35 +01:00
Clifford Wolf	fb4c3dff33	Added first presentation slides	2014-01-27 17:08:19 +01:00
Clifford Wolf	fa103e55ad	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	2014-01-26 02:29:19 +01:00
Clifford Wolf	fd6ca84f3c	Merge pull request #21 from hansiglaser/master ... beautified write_intersynth, enabled multiple "-map" for the extract pass	2014-01-25 17:28:17 -08:00
Johann Glaser	e9a2094774	enabled multiple "-map" for the extract pass	2014-01-25 21:11:34 +01:00
Johann Glaser	f13b3518aa	beautified write_intersynth	2014-01-25 20:16:38 +01:00
Ahmed Irfan	0325efe172	root bug corrected	2014-01-25 19:33:24 +01:00
Clifford Wolf	c1ed2607fb	Added support for // comments in liberty parser	2014-01-25 06:32:16 +01:00
Clifford Wolf	a139b49401	Merge branch 'btor'	2014-01-24 23:44:46 +01:00
Ahmed Irfan	137742786e	removed regex include	2014-01-24 18:04:37 +01:00
Ahmed Irfan	2e44b1b73a	merged clifford changes + removed regex	2014-01-24 17:35:42 +01:00
Clifford Wolf	210dda286f	Use techmap -share_map in btor scripts	2014-01-24 15:52:16 +01:00
Clifford Wolf	6804edd5d4	Moved btor scripts to backends/btor/	2014-01-24 15:48:07 +01:00
Clifford Wolf	da26bb4378	Restored Makefile	2014-01-24 15:47:09 +01:00
Clifford Wolf	ec167350b4	Restored IdString::check()	2014-01-24 15:46:41 +01:00
Clifford Wolf	d8300d1fb8	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor	2014-01-24 15:43:42 +01:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Ahmed Irfan	761b8f99d7	minor change in script	2014-01-24 15:00:43 +01:00
Ahmed Irfan	9d07d83c5a	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	2014-01-22 10:45:21 +01:00
Clifford Wolf	88fbdd4916	Fixed algorithmic complexity of AST simplification of long expressions	2014-01-20 20:25:20 +01:00
Ahmed Irfan	aa3cb20e1e	slice bug corrected	2014-01-20 18:35:52 +01:00
Ahmed Irfan	c347f2825f	assert feature	2014-01-20 10:45:02 +01:00
Ahmed Irfan	b7adf4c7a0	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	2014-01-20 09:58:04 +01:00
Clifford Wolf	32a91458a7	Added hilomap command	2014-01-19 21:58:58 +01:00
Clifford Wolf	03a876c7e8	Added sat -tempinduc and sat -prove-asserts	2014-01-19 16:35:17 +01:00
Clifford Wolf	c36bac0e10	Added $assert support to satgen	2014-01-19 15:37:56 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Ahmed Irfan	234d0d0e1c	script added	2014-01-18 21:54:52 +01:00
Ahmed Irfan	90483f489b	Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor	2014-01-18 19:45:16 +01:00
Clifford Wolf	3d7a1491aa	Fixed $lut simlib model for a wider range of tools	2014-01-18 19:31:40 +01:00
Clifford Wolf	13359d65ba	Fixed parsing of verilog macros at end of line	2014-01-18 19:22:20 +01:00
Clifford Wolf	2fbaaaca7a	More changes to simlib to make it friendlier to a wider range of tools	2014-01-18 19:13:43 +01:00
Clifford Wolf	4a9e133fab	Fixed a type in $mem model in simlib.v	2014-01-18 18:54:50 +01:00
Ahmed Irfan	b281e13263	Merge branch 'master' of https://github.com/ahmedirfan1983/yosys	2014-01-18 18:11:26 +01:00
Ahmed Irfan	1dd797ab09	Merge branch 'master' of https://github.com/cliffordwolf/yosys	2014-01-18 18:10:31 +01:00
Ahmed Irfan	da8af91552	pmux2mux	2014-01-18 17:29:55 +01:00
Clifford Wolf	bef17eeb10	Removed cases of trailing comma in stdcells.v	2014-01-18 15:36:17 +01:00
Clifford Wolf	5b96675696	Added $bu0 cell to simlib.v	2014-01-18 15:35:15 +01:00
Clifford Wolf	839af272ad	Improved setundef random number generator	2014-01-18 02:56:36 +01:00
Clifford Wolf	091d9abc3e	Added setundef command	2014-01-17 23:14:36 +01:00
Clifford Wolf	548d5aafa4	Some improvements in log_dump_val_worker() templates	2014-01-17 23:14:17 +01:00
Clifford Wolf	db9cf544b8	Added techlibs/common/pmux2mux.v	2014-01-17 20:06:15 +01:00
Ahmed Irfan	9a689f33a5	verilog default options pull ... shift operator width issues	2014-01-17 19:32:35 +01:00
Ahmed Irfan	fc3f2961be	Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor	2014-01-17 19:07:41 +01:00
Ahmed Irfan	f2ee57f798	Merge pull request #4 from cliffordwolf/master ... verilog defaults	2014-01-17 10:07:05 -08:00
Clifford Wolf	6170cfe9cd	Added verilog_defaults command	2014-01-17 17:22:29 +01:00
Clifford Wolf	2e370d5a2f	Added support for $adff with undef data inputs to opt_rmdff	2014-01-17 16:42:40 +01:00
Clifford Wolf	651ce67d97	Added select -assert-none and -assert-any	2014-01-17 16:34:50 +01:00
Ahmed Irfan	be7707c5cf	Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor	2014-01-17 10:50:59 +01:00