9 commits

Author	SHA1	Message	Date
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00
Clifford Wolf	c8763301b4	Added $div and $mod technology mapping	2013-08-09 17:09:24 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	ff4a1dd06c	Improved vcdcd.pl (added -d option)	2013-05-14 09:41:47 +02:00
Clifford Wolf	be8ecd6d16	Some improvements in vcdcd.pl	2013-05-14 08:50:59 +02:00
Clifford Wolf	2d9cbd3b02	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00