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Author SHA1 Message Date
Marcelina Kościelnicka
95a39d3425 kernel/mem: Add priority_mask to model. 
This is going to be used to store arbitrary priority masks in the
future.  Right now, it is not supported by our cell library, so the
priority_mask is computed from port order on helper construction,
and discarded when emitted.  However, this allows us to already convert
helper-using passes to the new model.
 2021-05-25 00:38:20 +02:00
Marcelina Kościelnicka
835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
dbfd0b61e3 hashlib: Add a hash for bool. 2021-05-24 22:02:15 +02:00
Marcelina Kościelnicka
5488c69d2a Add a .mailmap file. 2021-05-24 17:37:29 +02:00
Miodrag Milanović
c9dc7d5928
Merge pull request #2779 from YosysHQ/mwk/nuke-travis 
Remove Travis CI.
 2021-05-24 17:24:01 +02:00
Marcelina Kościelnicka
c3e65a4ce0 Remove Travis CI. 
It has been replaced by GitHub Actions, and travis-ci.org is shutting
down in a few days anyway.
 2021-05-24 17:18:03 +02:00
Marcelina Kościelnicka
b6721aa9d8 backend/firrtl: Convert to use Mem helpers. 2021-05-24 14:00:33 +02:00
Marcelina Kościelnicka
ef4ddfacf3 github actions: Test on several gcc and clang versions on Linux. 
Fixes #2776.
 2021-05-24 02:20:16 +02:00
Marcelina Kościelnicka
df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka
afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
33513d923a btor: Use is_mem_cell in one more place. 2021-05-23 20:34:52 +02:00
Marcelina Kościelnicka
d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka
1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka
039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
c7076495f1 kernel/mem: Add a check() function. 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
ff9e0394b8 kernel/mem: defer port removal to emit() 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Miodrag Milanović
9420bde09f
Run VS build on PRs and each push 2021-05-20 19:21:34 +02:00
Marcelina Kościelnicka
25de8faf10 Bump version 2021-05-20 12:50:32 +02:00
Marcelina Kościelnicka
4240498f71 tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
Miodrag Milanovic
d8c5d6815c Visual Studio build action 2021-05-17 10:24:30 +02:00
gatecat
34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Rupert Swarbrick
3421979f00 Change the type of current_module to Module 
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.

This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
 2021-05-13 23:44:48 -04:00
Rupert Swarbrick
51ed4a7149 Use range-based for loop in AST::process 
No functional change: just get rid of the explicit iterator and
replace (*it)-> with child->. It's even the same number of characters,
but is hopefully a little easier to read.
 2021-05-13 23:37:27 -04:00
Adam Greig
9e02786d39 Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. 2021-05-12 10:04:34 +01:00
Zachary Snow
4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka
32a0ce9d68 blif: Use library cells' start_offset and upto for wideports. 
Fixes #2729.
 2021-05-08 15:50:03 +02:00
Marcelina Kościelnicka
a6081b46ce connect: Add -assert option, fix non-working sigmap. 
Should be useful for writing tests.
 2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka
5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Miodrag Milanović
d061b0e41a
Merge pull request #2738 from mdko/xilinx-blif 
Fix use of blif name in synth_xilinx command
 2021-04-27 11:46:41 +02:00
Michael Christensen
67d6f3973b Fix use of blif name in synth_xilinx command 2021-04-27 02:29:52 -07:00
Claire Xen
86a6ac7623
Merge pull request #2737 from YosysHQ/claire/fix2736 
Remove duplicates from conns array in JSON front-end, fixes #2736
 2021-04-26 17:54:30 +02:00
Claire Xenia Wolf
58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 2021-04-26 16:32:12 +02:00
Claire Xen
a5adb00774
Merge pull request #2669 from YosysHQ/claire/ice40defaults 
Add input default assignments to iCE40 cell library
 2021-04-21 12:24:07 +02:00
Claire Xenia Wolf
46d3f03d27 Add default assignments to other SB_* simulation models 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-04-20 18:52:36 +02:00
Claire Xenia Wolf
8aee80040d Add default assignments to SB_LUT4 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-04-20 12:46:21 +02:00
Lofty
dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Stefan Riesenberger
a58571d0fe sf2: fix name of AND modules 2021-04-09 16:46:05 +02:00
whitequark
0b05452cf7
Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memid 
flatten: rewrite memid in memwr actions
 2021-04-09 14:22:36 +00:00
whitequark
c5c57e3f5e flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
Zachary Snow
0ccc7229c0 preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
Marcelina Kościelnicka
b7ea71e6e3 equiv: Suggest running async2sync or clk2fflogic where appropriate. 
See #2713.
 2021-03-30 18:20:21 +02:00
Zachary Snow
ba2ff1ea98 verilog: revise hot comment warnings 2021-03-30 09:21:18 -04:00
Eddie Hung
8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695) 
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
 2021-03-29 22:02:06 -07:00
Eddie Hung
55dc5a4e4f
abc9: fix SCC issues (#2694) 
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
 2021-03-29 22:01:57 -07:00