Eddie Hung
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Miodrag Milanovic
70db8e9200
Prevent double error message
2020-02-17 16:46:34 +01:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
Miodrag Milanovic
d8735b2913
Add to changelog
2020-02-17 15:08:35 +01:00
Miodrag Milanovic
be977cf7eb
No new error if already failing
2020-02-17 12:54:36 +01:00
R. Ou
13d0ff4a5f
coolrunner2: Use extract_counter to optimize counters
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This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
2020-02-17 03:09:40 -08:00
R. Ou
fec7dc5c9e
extract_counter: Implement extracting up counters
2020-02-17 03:08:52 -08:00
R. Ou
940bab6841
extract_counter: Add support for inverted clock enable
2020-02-17 03:08:52 -08:00
R. Ou
5fc180ed2d
extract_counter: Fix clock enable
2020-02-17 03:08:52 -08:00
R. Ou
12fa4a3121
extract_counter: Fix outputting count to module port
2020-02-17 03:08:52 -08:00
R. Ou
508f1ff6a1
extract_counter: Allow forbidding async reset
2020-02-17 03:08:52 -08:00
R. Ou
7b922c0d89
extract_counter: Refactor out extraction settings into struct
2020-02-17 03:08:52 -08:00
Jeff Wang
1c16311d10
update documentation for enums and typedefs
2020-02-17 04:42:55 -05:00
Jeff Wang
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Jeff Wang
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
R. Ou
6a0682f5a0
coolrunner2: Separate and improve buffer cell insertion pass
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The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
Marcin Kościelnicki
cd60f079d6
tests/aiger: Add missing .gitignore
2020-02-15 19:52:21 +01:00
Tim 'mithro' Ansell
b9dfdbbfee
show: Add -nobg argument.
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Makes yosys wait for the viewer command to finish before continuing.
2020-02-15 14:03:16 +01:00
Miodrag Milanović
2baa6d799e
Merge pull request #1706 from YosysHQ/mmicko/remove_executable_flag
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Remove executable flag from files
2020-02-15 11:15:35 +01:00
Miodrag Milanovic
cd5c177739
Remove executable flag from files
2020-02-15 10:36:44 +01:00
Miodrag Milanović
a7df492243
Add comment for macOS dependency install
2020-02-15 09:44:32 +01:00
Eddie Hung
f9f86fd758
Revert "abc9: fix abc9_arrival for flops"
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This reverts commit f7c0dbecee
2020-02-14 16:08:04 -08:00
Miodrag Milanovic
6b396e6455
remove whitespace
2020-02-14 13:12:05 +01:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test
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make rpc frontend unix socket test less fragile
2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
0cf7598cd6
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
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Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
2020-02-13 17:32:54 -08:00
Eddie Hung
8c4c546009
Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init
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iopadmap: move \init attributes from outpad output to its input
2020-02-13 17:32:14 -08:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
Eddie Hung
3d2a2e8799
iopadmap: fixes as suggested by @mwkmwkmwk
2020-02-13 14:57:06 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
Eddie Hung
f5cc8cfa79
write_xaiger: default value for abc9_init
2020-02-13 12:37:17 -08:00
Eddie Hung
f7c0dbecee
abc9: fix abc9_arrival for flops
2020-02-13 12:34:09 -08:00
Eddie Hung
00d41905df
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
2020-02-13 12:33:58 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55
make rpc frontend unix socket test less fragile
2020-02-13 20:52:22 +01:00
Claire Wolf
cb7bc6a12f
Merge pull request #1694 from rqou/json_compat_fix
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json: Change compat mode to directly emit ints <= 32 bits
2020-02-13 18:30:22 +01:00
Miodrag Milanovic
0ba2a2b1fa
Add new logger pass
2020-02-13 13:35:29 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Eddie Hung
c244b27b6d
abc9: cleanup
2020-02-10 10:17:23 -08:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master
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$readmem[hb] file inclusion is now relative to the Verilog file
2020-02-10 08:31:01 -08:00
N. Engelhardt
224dc033aa
Merge pull request #1669 from thasti/pyosys-attrs
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Make RTLIL attributes accessible via pyosys
2020-02-10 12:38:28 +01:00
whitequark
7cc9d487ff
Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset
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manual: explain RTLIL::Wire::{upto,offset}
2020-02-09 20:29:16 +00:00
whitequark
161eba253f
manual: explain RTLIL::Wire::{upto,offset}.
2020-02-09 14:54:07 +00:00
R. Ou
20ce4118da
json: Change compat mode to directly emit ints <= 32 bits
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This increases compatibility with certain older parsers in some cases
that worked before commit 15fae357
2020-02-09 01:01:18 -08:00
