220 commits

Author	SHA1	Message	Date
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	0b8b8d41eb	Fixed build with gcc-4.6	2014-08-07 22:37:01 +02:00
Clifford Wolf	2501abe1ee	Various fixes and improvements in wreduce pass	2014-08-05 19:01:41 +02:00
Clifford Wolf	5b3dc07b9a	Removed old "constmap" from wreduce code	2014-08-05 16:53:53 +02:00
Clifford Wolf	523df73145	Added support for truncating of wires to wreduce pass	2014-08-05 14:47:03 +02:00
Clifford Wolf	d3b1a29708	Cleanups and improvements in wreduce pass	2014-08-05 13:11:04 +02:00
Clifford Wolf	1c182cedb7	Added mux support to wreduce command	2014-08-05 12:49:53 +02:00
Clifford Wolf	0bb6942218	Added "show -signed"	2014-08-04 15:40:08 +02:00
Clifford Wolf	ebbbe7fc83	Added RTLIL::IdString::in(...)	2014-08-04 15:40:07 +02:00
Clifford Wolf	027376515a	Progress in "wreduce" pass	2014-08-03 20:02:42 +02:00
Clifford Wolf	0b02f6ca30	Added "wreduce" command (work in progress)	2014-08-03 15:02:05 +02:00
Clifford Wolf	9bb5298c10	Fixes in show command (related to new IdString)	2014-08-03 12:40:23 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	d13eb7e099	Added ModIndex helper class, some changes to RTLIL::Monitor	2014-08-01 17:14:32 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	b5a9e51b96	Added "trace" command	2014-07-31 15:02:16 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	6400ae3648	Added write_file command	2014-07-30 19:59:29 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	5826670009	Various RTLIL::SigSpec related code cleanups	2014-07-25 14:25:42 +02:00
Clifford Wolf	c4e4f79a2a	Disabled cover() for non-linux builds	2014-07-25 12:27:36 +02:00
Clifford Wolf	91bf0c90c8	Improvements in "cover" command	2014-07-25 12:04:40 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	2f54345cff	Added "cover" command	2014-07-24 16:14:19 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	1ce5e83555	Added "select -assert-count"	2014-07-20 20:15:49 +02:00
Clifford Wolf	44f13aff92	Improved seeding of color rng in show command	2014-07-18 16:44:45 +02:00
Clifford Wolf	22a998903b	Added %D and %c select commands	2014-06-14 16:19:32 +02:00
Clifford Wolf	7020f7fc13	added tee cmd	2014-06-03 09:23:31 +02:00
Clifford Wolf	f69b5800c9	fixed syntax error in dot file created by "show" command	2014-05-10 16:22:56 +02:00