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Author	SHA1	Message	Date
Akash Levy	953f405a84	Merge branch 'YosysHQ:main' into master	2024-08-07 11:47:52 -07:00
Martin Povišer	b1569de537	Merge pull request #4527 from povik/exec-newline ... exec: Add missing newline	2024-08-07 13:04:48 +02:00
Martin Povišer	4c3203866f	exec: Add missing newline	2024-08-07 13:02:00 +02:00
github-actions[bot]	669f8b18f0	Bump version	2024-08-07 00:18:20 +00:00
Akash Levy	31d8d5de41	Merge branch 'YosysHQ:main' into master	2024-08-06 03:06:59 -07:00
Akash Levy	68b3ad4bd3	Display resource sharing count	2024-08-06 02:27:09 -07:00
Akash Levy	36fb6e08c1	Make muxpack faster	2024-08-06 02:26:57 -07:00
Akash Levy	7f5dcd270d	Merge branch 'YosysHQ:main' into master	2024-08-06 01:01:08 -07:00
Miodrag Milanovic	d08bf671b2	Next dev cycle	2024-08-06 09:48:35 +02:00
Miodrag Milanovic	80ba43d262	Release version 0.44	2024-08-06 09:42:28 +02:00
Miodrag Milanović	e5d8505349	Merge pull request #4523 from YosysHQ/emil/no-lto-lld ... Makefile: no LTO and lld by default	2024-08-06 09:08:09 +02:00
github-actions[bot]	d2b5788674	Bump version	2024-08-06 00:18:14 +00:00
Akash Levy	24f38678ac	NDEBUG doesn't do anything	2024-08-05 16:46:00 -07:00
Akash Levy	b4ae5e8574	Merge branch 'YosysHQ:main' into master	2024-08-05 11:02:17 -07:00
Emil J. Tywoniak	eeecb54532	Makefile: no LTO and lld by default	2024-08-05 19:28:09 +02:00
N. Engelhardt	01b99972b4	Merge pull request #4518 from YosysHQ/micko/sim_signal_names ... Set ranges on exported wires in VCD and FST	2024-08-05 15:03:59 +02:00
Miodrag Milanovic	6d98418f3d	Set ranges on exported wires in VCD and FST	2024-08-02 15:23:00 +02:00
Akash Levy	f7ffd73fa0	Fix opt_dff problem	2024-08-01 09:20:18 -07:00
Akash Levy	76db4e390b	Smalledit	2024-08-01 00:04:50 -07:00
Akash Levy	9873315caa	Update Verific	2024-07-31 22:40:15 -07:00
Akash Levy	c2da53be50	Fix gitignore	2024-07-30 23:10:28 -07:00
Akash Levy	bafce0ddee	Revert SCC	2024-07-30 23:08:06 -07:00
Akash Levy	c0af4604bc	Update Yosys	2024-07-30 16:55:18 -07:00
github-actions[bot]	c788484679	Bump version	2024-07-30 00:18:19 +00:00
Miodrag Milanović	3e14e67374	Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase ... VHDL is case insensitive, make sure netlist name is proper	2024-07-29 16:44:13 +02:00
Emil J	92cac63845	Merge pull request #4344 from widlarizer/emil/keep_hierarchy ... cost: add keep_hierarchy pass with min_cost argument	2024-07-29 16:33:08 +02:00
Miodrag Milanovic	405897a971	Update top value that is returned back to hierarchy pass	2024-07-29 15:50:38 +02:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp ... Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
N. Engelhardt	7c3666ff68	Merge pull request #4505 from YosysHQ/micko/ext_register ... Initialize extensions when Verific pass is registered	2024-07-29 15:23:31 +02:00
Emil J	e21dd292fc	Merge pull request #4502 from YosysHQ/emil/build-opt-levels ... Release build configuration improvements	2024-07-29 15:13:52 +02:00
Emil J. Tywoniak	af0c2fa659	Brewfile: add llvm for lld	2024-07-29 15:13:24 +02:00
Emil J	051d83205d	Merge pull request #4471 from georgerennie/hashlib_primes ... hashlib: Add some more primes	2024-07-29 15:10:22 +02:00
Martin Povišer	61ae9f4e07	Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2 ... proc_rom: test src attribute on memories	2024-07-29 13:58:19 +02:00
Emil J. Tywoniak	4b29f64142	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
Emil J	49eaa108a5	Merge pull request #4425 from YosysHQ/emil/doc-sigmap ... sigmap: comments	2024-07-29 10:18:44 +02:00
Emil J. Tywoniak	01fd72520f	proc_rom: test src attribute on memories	2024-07-29 10:13:45 +02:00
Akash Levy	89630d3755	Merge branch 'YosysHQ:main' into master	2024-07-28 22:42:33 -07:00
github-actions[bot]	960bca0196	Bump version	2024-07-27 00:17:35 +00:00
Martin Povišer	ced1313193	Merge pull request #4510 from JamesTimothyMeech/patch-1 ... Update interactive_investigation.rst	2024-07-26 15:17:57 +02:00
James Meech	1c41db6978	Update interactive_investigation.rst ... The text starting at line 118 refers to proc twice but it should refer to opt and then to proc.	2024-07-26 13:53:08 +01:00
N. Engelhardt	dd3637f9f0	Merge pull request #4506 from povik/synthprop-formatting ... synthprop: Reformat the help	2024-07-26 12:28:09 +02:00
N. Engelhardt	41b51c1ca9	Merge pull request #4503 from RCoeurjoly/vhdl_extension ... Guess VHDL frontend for both *.vhd and *vhdl files	2024-07-26 10:44:10 +02:00
github-actions[bot]	610d27dc1c	Bump version	2024-07-26 00:17:42 +00:00
Martin Povišer	7ee685a0b0	proc_rom: Set src on the emitted memory	2024-07-25 23:14:27 +01:00
Akash Levy	f790b75c19	Don't preserve user nets and update Verific tree balancing	2024-07-25 06:01:06 -07:00
Akash Levy	0a997b9e64	muxpack verbosity and -ignore_excl option	2024-07-25 04:40:37 -07:00
Martin Povišer	e063b96104	synthprop: Reformat the help	2024-07-25 11:43:58 +02:00
Miodrag Milanovic	9566709426	Initialize extensions when verific pass is registered	2024-07-25 11:25:17 +02:00
Emil J. Tywoniak	7cd27e1182	Makefile: remove accidental abc opt level override for wasi builds	2024-07-24 21:31:35 +02:00
Emil J. Tywoniak	29d53bc94a	actions: try fix GITHUB_PATH	2024-07-24 19:50:34 +02:00