12 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	4cbc92f50f	quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged	2025-03-11 10:35:31 +01:00
Emil J. Tywoniak	62885f1de3	quicklogic: ql_dsp_simd remove unused MODE_BITS packing	2025-03-11 10:35:31 +01:00
Emil J. Tywoniak	9b52ba8738	quicklogic: ql_dsp_simd add dspv2 support, fix dspv1	2025-03-11 10:35:31 +01:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int ... `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Miodrag Milanovic	627fbc3477	Fix Windows build by forcing initialization order, fixes #4068	2024-01-02 11:26:48 +01:00
Martin Povišer	7d738b07da	ql_dsp_*: Clean up ... Clean up the code up to Yosys standards. Drop detection of QL_DSP2_MULTADD in io_regs since those cells can't be inferred with the current flow anyway.	2023-12-04 15:52:02 +01:00
N. Engelhardt	20d864bbde	add dsp inference	2023-12-04 15:52:02 +01:00