3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 11:55:52 +00:00
Commit graph

7 commits

Author SHA1 Message Date
Krystine Sherwin
2d6738bb10
qlf_tests: minor adjustment
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 09:38:48 +13:00
N. Engelhardt
c2fc33f0eb fix test setup for synth_quicklogic memory tests 2023-12-01 14:03:07 +01:00
Krystine Sherwin
5634d98ccb
attempting to sim split memory tests
and failing
2023-12-01 21:16:58 +13:00
Krystine Sherwin
d9d54e66c7
QLF_TDP36K: asymmetric simulation tests 2023-12-01 20:47:39 +13:00
Krystine Sherwin
0cd4a10c81
QLF_TDP36K: truncation tests matter
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-01 17:14:01 +13:00
Krystine Sherwin
7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-01 17:00:15 +13:00
Krystine Sherwin
7a659bdd26
QLF_TDP36K: parameterised sim test gen
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-01 16:26:00 +13:00