16 commits

Author	SHA1	Message	Date
Robert O'Callahan	8b75c06141	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
Miodrag Milanovic	e6f7cf3b29	Update tests	2023-06-09 14:41:45 +02:00
Icenowy Zheng	c2b7ad3b28	anlogic: support BRAM mapping ... Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>	2021-12-17 20:28:22 +08:00
Marcelina Kościelnicka	18806f1ef6	memory_bram: Reuse extract_rdff helper for make_outreg. ... Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.	2021-05-25 22:42:03 +02:00
Xiretza	acd47bbd52	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
Marcelina Kościelnicka	9a4f420b4b	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka	3050454d6e	anlogic: Use dfflegalize.	2020-07-14 05:02:50 +02:00
Eddie Hung	317c18fc6f	Simplify breaking tests/arch/*/fsm.ys tests	2020-03-20 11:25:17 -07:00
Eddie Hung	c082329af3	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
Eddie Hung	caab66111e	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
Miodrag Milanovic	3e0ffe05a7	Fixed tests	2019-11-11 15:41:33 +01:00
Miodrag Milanovic	12383f37b2	Common memory test now shared	2019-10-18 12:33:35 +02:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	56f9482675	Fix path to yosys	2019-10-18 11:12:03 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00