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mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
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592 commits 92 branches 52 tags 62 MiB
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4 commits

Author SHA1 Message Date
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 95dbacefbf Fixed bug in synthesis of memories that are never written 2013-10-17 21:00:37 +02:00
Clifford Wolf f3a849512f Added help messages to memory_* passes 2013-03-01 10:17:35 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00