10 commits

Author	SHA1	Message	Date
Eddie Hung	a7a88109f5	Update comment on boxes	2019-06-26 20:00:15 -07:00
Eddie Hung	480a04cb3c	Realistic delays for RAM32X1D too	2019-06-25 09:34:28 -07:00
Eddie Hung	6095357390	Add RAM32X1D box info	2019-06-25 09:34:19 -07:00
Eddie Hung	2f770b7400	Use LUT delays for dist RAM delays	2019-06-24 23:02:53 -07:00
Eddie Hung	152e682bd5	Add Xilinx dist RAM as comb boxes	2019-06-24 21:54:01 -07:00
Eddie Hung	792d0670c3	Add comment to xc7 box	2019-06-22 14:28:24 -07:00
Eddie Hung	7903ebe3e0	Carry in/out box ordering now move to end, not swap with end	2019-06-22 14:18:42 -07:00
Eddie Hung	65c022c257	Remove DFF and RAMD box info for now	2019-06-21 20:41:14 -07:00
Eddie Hung	8fa74287a7	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
Eddie Hung	d47ff7ba87	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00

Renamed from techlibs/xilinx/abc.box (Browse further)