Jim Lawson
e8341d949f
Merge remote-tracking branch 'upstream/master'
2019-07-30 16:04:27 -07:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
Eddie Hung
b4f38cca77
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
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verilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-29 09:16:09 -07:00
David Shah
ccf759864a
Merge pull request #1234 from mmicko/fix_gzip_no_exist
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Fix case when file does not exist
2019-07-29 15:50:20 +01:00
Miodrag Milanovic
3e4307c104
Fix case when file does not exist
2019-07-29 12:29:13 +02:00
Clifford Wolf
5be5bd0fb6
Update README to use "read" instead of "read_verilog"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-29 10:40:30 +02:00
Clifford Wolf
fc462c8243
Call "read_verilog" with -defer from "read"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-29 10:29:36 +02:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
David Shah
6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip
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Add support for gzip'd input files
2019-07-27 07:40:38 +01:00
David Shah
482926cbd3
Update CHANGELOG
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 15:53:21 +01:00
David Shah
92694ea3a9
verilog_lexer: Increase YY_BUF_SIZE to 65536
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 13:35:39 +01:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
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This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
David Shah
da6701c4cd
Fix frontend auto-detection for gzipped input
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:29:05 +01:00
David Shah
933db0410e
Add support for reading gzip'd input files
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Eddie Hung
a02d1720a7
Merge branch 'master' of github.com:YosysHQ/yosys
2019-07-25 10:49:26 -07:00
Eddie Hung
c5e31ac9c3
Bump abc to fix &mfs bug
2019-07-25 10:48:58 -07:00
Clifford Wolf
eb663c7579
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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intel: Make -noiopads the default
2019-07-25 17:19:54 +02:00
Clifford Wolf
2bdd8003d3
Merge pull request #1219 from jakobwenzel/objIterator
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made ObjectIterator comply with Iterator Interface
2019-07-25 17:19:11 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 06:44:17 -07:00
Jakob Wenzel
70882a8070
replaced std::iterator with using statements
2019-07-25 09:51:09 +02:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Jim Lawson
7e298084e4
Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend.
2019-07-24 13:33:16 -07:00
Eddie Hung
d6a289d3e3
Merge pull request #1222 from koriakin/s6-example
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Add a simple example for Spartan 6
2019-07-24 10:51:03 -07:00
Jim Lawson
c66b7402c0
Merge remote-tracking branch 'upstream/master'
2019-07-24 10:20:46 -07:00
Marcin Kościelnicki
173c975894
Add a simple example for Spartan 6
2019-07-24 18:59:03 +02:00
Jakob Wenzel
25685a9a5b
made ObjectIterator extend std::iterator
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this makes it possible to use std algorithms on them
2019-07-24 16:35:40 +02:00
Dan Ravensloft
49528ed3bd
intel: Make -noiopads the default
2019-07-24 10:38:15 +01:00
Dan Ravensloft
67b4ce06e0
intel: Map M9K BRAM only on families that have it
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This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
Eddie Hung
a66f17b6a7
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
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ice40: Fix SB_MAC16 sim model for signed modes
2019-07-23 09:56:58 -07:00
Eddie Hung
be3d9c8eaa
Merge pull request #1214 from jakobwenzel/astmod_clone
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initialize noblackbox and nowb in AstModule::clone
2019-07-22 07:42:53 -07:00
Jakob Wenzel
e2fe8e0a4f
initialize noblackbox and nowb in AstModule::clone
2019-07-22 10:37:40 +02:00
Clifford Wolf
c6d8692c97
Add "stat -tech cmos"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-20 15:06:28 +02:00
Eddie Hung
09beeee38a
Try and fix again
2019-07-19 14:40:57 -07:00
Eddie Hung
c926eeb43a
Add another test
2019-07-19 14:02:46 -07:00
Eddie Hung
cb0fd05215
Do not access beyond bounds
2019-07-19 13:58:50 -07:00
Eddie Hung
54708dfbd7
Add an SigSpec::at(offset, defval) convenience method
2019-07-19 13:54:57 -07:00
Eddie Hung
3a87dc3524
Wrap A and B in sigmap
2019-07-19 13:23:07 -07:00
Eddie Hung
31b0002e8c
Remove "top" from message
2019-07-19 13:20:45 -07:00
Eddie Hung
bcd8027182
Also optimise MSB of $sub
2019-07-19 13:11:48 -07:00
Eddie Hung
5bd088a686
Add one more test with trimming Y_WIDTH of $sub
2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df
Be more explicit
2019-07-19 12:53:18 -07:00
Eddie Hung
fc0e36d1c0
wreduce for $sub
2019-07-19 12:50:21 -07:00
Eddie Hung
4e9b1d36fa
Add tests for sub too
2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2
Add test
2019-07-19 12:43:02 -07:00
Eddie Hung
25ff27e37f
SigSpec::extract to take negative lengths
2019-07-19 12:34:04 -07:00
David Shah
80884d6f7b
ice40: Fix test_dsp_model.sh
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:57 +01:00
David Shah
79f14c7514
ice40/cells_sim.v: Fix sign of J and K partial products
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:41 +01:00
David Shah
3c84271543
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73
Add tests for all combinations of A and B signedness for comb mul
2019-07-19 08:52:49 -07:00
