mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-11 17:54:44 +00:00
Code Activity
9409 commits 117 branches 54 tags 57 MiB
Commit graph

3 commits

Author SHA1 Message Date
Dan Ravensloft
3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Dan Ravensloft
43cc6bd8a1 synth_intel_alm: VQM support 2020-04-15 16:15:25 +02:00
Dan Ravensloft
2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00