mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 08:23:19 +00:00
Code Activity
15324 commits 116 branches 56 tags 64 MiB
Commit graph

2 commits

Author SHA1 Message Date
Dan Ravensloft
1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
Dan Ravensloft
b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00