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Author	SHA1	Message	Date
Clifford Wolf	dbb2f755c1	Merge pull request #363 from rqou/master ... Miscellaneous build tweaks	2017-07-18 15:21:12 +02:00
Robert Ou	85d667ca08	makefile: Add the option to use libtermcap	2017-07-17 14:21:59 -07:00
Robert Ou	f0741698fa	Fix build warnings for win64 ... Win64 has a 32-bit long. Use intptr_t to work on any data model.	2017-07-17 12:36:43 -07:00
Clifford Wolf	c00d8a5b73	Add $alu to list of supported cells for "stat -width"	2017-07-14 11:32:49 +02:00
Clifford Wolf	10c7709e68	Generate FSM-style testbenches in smtbmc	2017-07-12 15:57:04 +02:00
Clifford Wolf	4a8c131fa7	Fix the fixed handling of x-bits in EDIF back-end	2017-07-11 17:45:29 +02:00
Clifford Wolf	479be3cec7	Fix handling of x-bits in EDIF back-end	2017-07-11 17:38:19 +02:00
Clifford Wolf	9557fd2a36	Add attributes and parameter support to JSON front-end	2017-07-10 13:17:38 +02:00
Clifford Wolf	8a69759306	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
Clifford Wolf	4b2d1fe688	Add JSON front-end	2017-07-08 16:40:40 +02:00
Clifford Wolf	3c693b6561	Change s/asserts/assertions/ in yosys-smtbmc log messages	2017-07-07 11:52:25 +02:00
Clifford Wolf	8f7404f82c	Add "yosys-smtbmc --presat"	2017-07-07 02:47:30 +02:00
Clifford Wolf	5442554e6f	Fix generation of multiple outputs for same AIG node in write_aiger	2017-07-05 14:23:54 +02:00
Clifford Wolf	37af6294bd	Add write_table command	2017-07-05 12:13:53 +02:00
Clifford Wolf	28039c3063	Add Verific Release information to log	2017-07-04 20:01:30 +02:00
Clifford Wolf	621787a9e0	Fix some c++ clang compiler errors	2017-07-03 19:38:30 +02:00
Clifford Wolf	5c1c126374	Apply minor coding style changes to coolrunner2 target	2017-07-03 19:35:40 +02:00
Clifford Wolf	6afee022ad	Merge pull request #352 from rqou/master ... Initial Coolrunner-II support	2017-07-03 19:33:36 +02:00
Clifford Wolf	3f863c607a	Merge pull request #356 from set-soft/clean-test ... Added the test outputs to the clean target	2017-07-03 19:33:25 +02:00
Clifford Wolf	d223292aa9	Merge pull request #355 from set-soft/exclude_TBUF_merge ... Excluded $_TBUF_ from opt_merge pass	2017-07-03 19:31:59 +02:00
Salvador E. Tropea	fb30511044	Added the test outputs to the clean target	2017-07-03 13:33:11 -03:00
Salvador E. Tropea	ca23554528	Excluded $_TBUF_ from opt_merge pass	2017-07-03 13:21:20 -03:00
Clifford Wolf	3e0948e16f	Remove unneeded delays in smtbmc vlogtb	2017-07-03 15:37:17 +02:00
Clifford Wolf	287831dca3	Include output ports with constant driver in AIGER output	2017-07-03 14:53:17 +02:00
Clifford Wolf	ea805af6f5	Add "yosys-smtbmc --vlogtb-top"	2017-07-01 18:19:23 +02:00
Clifford Wolf	0a02cdb93b	Fix and_or_buffer optimization in opt_expr for signed operators	2017-07-01 16:05:26 +02:00
Clifford Wolf	7d2fb6e2fc	Fix smtbmc vlogtb bug in $anyseq handling	2017-07-01 02:13:32 +02:00
Clifford Wolf	0f217080cf	Add "design -import"	2017-06-30 19:18:52 +02:00
Clifford Wolf	8952bd6f45	Add chtype command	2017-06-30 17:57:34 +02:00
Clifford Wolf	18c030a8c9	Add $tribuf to opt_merge blacklist	2017-06-30 17:44:44 +02:00
Clifford Wolf	5b95901a1e	Merge pull request #353 from azonenberg/master ... greenpak4_counters: Use more human-readable names for inferred counters	2017-06-27 19:18:32 +02:00
Robert Ou	b102c0e254	coolrunner2: Add a few more primitives ... These cannot be inferred yet, but add them to cells_sim.v for now	2017-06-25 23:58:28 -07:00
Robert Ou	36b75dfcb7	coolrunner2: Initial mapping of latches	2017-06-25 23:58:28 -07:00
Robert Ou	4af5baab21	coolrunner2: Initial mapping of DFFs ... All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)	2017-06-25 23:58:28 -07:00
Robert Ou	1eb5dee799	coolrunner2: Remove redundant INVERT_PTC	2017-06-25 23:58:28 -07:00
Robert Ou	ffff001008	coolrunner2: Remove debug prints	2017-06-25 23:58:28 -07:00
Robert Ou	5798105d47	coolrunner2: Correctly handle $_NOT_ after $sop	2017-06-25 23:58:28 -07:00
Robert Ou	908ce3fdce	coolrunner2: Also construct the XOR cell in the macrocell	2017-06-25 23:58:28 -07:00
Robert Ou	a64b56648d	coolrunner2: Initial techmapping for $sop	2017-06-25 23:58:22 -07:00
Andrew Zonenberg	cbdddc3af9	greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included	2017-06-24 14:54:07 -07:00
Robert Ou	6e0fb889fa	coolrunner2: Initial commit	2017-06-24 07:22:56 -07:00
Clifford Wolf	155a80dfb7	Fix handling of init values in "abc -dff" and "abc -clk"	2017-06-20 15:32:23 +02:00
Clifford Wolf	1f517d2b96	Fix history namespace collision	2017-06-20 05:26:12 +02:00
Clifford Wolf	c0ca99483c	Store command history when terminating with an error	2017-06-20 04:41:58 +02:00
Clifford Wolf	f6421c83a2	Switched abc "clock domain not found" error to log_cmd_error()	2017-06-20 04:22:34 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	0290b68a44	Update ABC to hg rev efbf7f13ea9e	2017-05-31 11:55:37 +02:00
Clifford Wolf	e7a984a4df	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
Clifford Wolf	c365e33fd7	Fix AIGER back-end for multiple symbols per input/latch/output/property	2017-05-30 19:09:11 +02:00