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16047 commits 122 branches 59 tags 73 MiB
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229 commits

Author SHA1 Message Date
Zachary Snow
b1a8e73a60 sv: fix some edge cases for unbased unsized literals 
- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
 2021-03-06 15:20:34 -05:00
Zachary Snow
d738b2c127 sv: support for parameters without default values 
- Modules with a parameter without a default value will be automatically
  deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
  just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
 2021-03-02 10:43:53 -05:00
Marcelina Kościelnicka
f4f471f342 frontend: Make helper functions for printing locations. 2021-02-23 23:51:52 +01:00
Marcelina Kościelnicka
a4c04d1b90 ast: fix dump_vlog display of casex/casez 
The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
 2021-01-29 16:28:15 +01:00
Julius Roob
2e23dfd96b Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
Udi Finkelstein
b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
Kazuki Sakamoto
185bbbe681 static cast: support changing size and signedness 
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
 2020-06-19 17:39:20 -07:00
Peter Crozier
f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Peter Crozier
0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Claire Wolf
589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
9f1fb11b1d Clear current_scope when done with RTLIL generation, fixes #1837 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-22 14:51:20 +02:00
Marcelina Kościelnicka
06a344efcb ilang, ast: Store parameter order and default value information. 
Fixes #1819, #1820.
 2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
whitequark
41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute. 
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
 2020-04-18 03:47:28 +00:00
Claire Wolf
e1fb12a4b9 Add LookaheadRewriter for proper bitselwrite support 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-16 12:11:07 +02:00
David Shah
4d02505820 ast: Fix handling of identifiers in the global scope 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 10:30:07 +01:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to fixup_ports(). 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
Alberto Gonzalez
6040593994
Revert over-aggressive change to a more modest cleanup. 2020-03-27 09:46:40 +00:00
Peter Crozier
6cad865d12 Simplify was not being called for packages. Broke typedef enums. 2020-03-22 18:20:46 -07:00
Alberto Gonzalez
eb30d66d01
Clean up pseudo-private member usage in frontends/ast/ast.cc. 2020-03-19 07:29:00 +00:00
Eddie Hung
4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Eddie Hung
e79376d6cb ast: quiet down when deriving blackbox modules 2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Jeff Wang
d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Jeff Wang
16ea4ea61a partial rebase of PeterCrozier's enum work onto current master 
I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.

Original commit:
"Initial implementation of enum, typedef, import.  Still a WIP."
881833aa73
 2020-01-16 13:51:47 -05:00
Clifford Wolf
e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
David Shah
f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Eddie Hung
0a1af434e8 Fix for svinterfaces 2019-09-30 14:52:04 -07:00
Eddie Hung
08b55a20e3 module->derive() to be lazy and not touch ast if already derived 2019-09-30 14:11:01 -07:00
Clifford Wolf
8da0888bf6 Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-20 12:16:20 +02:00
Eddie Hung
83ffec26cb Remove newline 2019-08-29 09:08:58 -07:00
Eddie Hung
6510297712 Restore non-deferred code, deferred case to ignore non constant attr 2019-08-29 09:02:10 -07:00
Eddie Hung
34ae29295d read_verilog -defer should still populate module attributes 2019-08-28 19:59:09 -07:00
Jakob Wenzel
24971fda87 handle real values when deriving ast modules 2019-08-19 14:17:36 +02:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Eddie Hung
9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung
6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Jakob Wenzel
e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
Clifford Wolf
ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf
a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00