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3 commits

Author SHA1 Message Date
Rupert Swarbrick
1aab608cff Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00