13 commits

Author	SHA1	Message	Date
Robert Ou	78fd24f40f	coolrunner2: Add INVERT parameter to some BUFGs	2017-08-14 12:13:33 -07:00
Robert Ou	1e3ffd57cb	coolrunner2: Add FFs with clock enable to cells_sim.v	2017-08-14 12:13:25 -07:00
Clifford Wolf	621787a9e0	Fix some c++ clang compiler errors	2017-07-03 19:38:30 +02:00
Clifford Wolf	5c1c126374	Apply minor coding style changes to coolrunner2 target	2017-07-03 19:35:40 +02:00
Robert Ou	b102c0e254	coolrunner2: Add a few more primitives ... These cannot be inferred yet, but add them to cells_sim.v for now	2017-06-25 23:58:28 -07:00
Robert Ou	36b75dfcb7	coolrunner2: Initial mapping of latches	2017-06-25 23:58:28 -07:00
Robert Ou	4af5baab21	coolrunner2: Initial mapping of DFFs ... All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)	2017-06-25 23:58:28 -07:00
Robert Ou	1eb5dee799	coolrunner2: Remove redundant INVERT_PTC	2017-06-25 23:58:28 -07:00
Robert Ou	ffff001008	coolrunner2: Remove debug prints	2017-06-25 23:58:28 -07:00
Robert Ou	5798105d47	coolrunner2: Correctly handle $_NOT_ after $sop	2017-06-25 23:58:28 -07:00
Robert Ou	908ce3fdce	coolrunner2: Also construct the XOR cell in the macrocell	2017-06-25 23:58:28 -07:00
Robert Ou	a64b56648d	coolrunner2: Initial techmapping for $sop	2017-06-25 23:58:22 -07:00
Robert Ou	6e0fb889fa	coolrunner2: Initial commit	2017-06-24 07:22:56 -07:00