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6 commits

Author SHA1 Message Date
Eddie Hung
8aab7fe7e6 Fix SRL16/32 techmap off-by-one 2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de synth_xilinx to call shregmap with enable support 2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0 synth_xilinx to use shregmap with -params too 2019-02-28 10:21:05 -08:00
Eddie Hung
c29f0c5048 Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 2019-02-28 09:31:24 -08:00
Tim 'mithro' Ansell
d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf
d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Renamed from techlibs/xilinx/cells.v (Browse further)